Datasheet > HSP43481GM-25/883

HSP43481GM-25/883

更新时间： 2024-11-13 22:09:47

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
2页	37K
描述
Digital Filter

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HSP43481GM-25/883 数据手册

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HSP43481/883

Digital Filter

August 1999

Features

Description

• This Circuit is Processed in Accordance to MIL-STD- The HSP43481/883 is a video-speed Digital Filter (DF)

883 and is Fully Conformant Under the Provisions of

Paragraph 1.2.1.

designed to efficiently implement vector operations such as

FIR digital filters. It is comprised of four filter cells cascaded

internally and a shift-and- add output stage, all in a single

integrated circuit. Each filter cell contains an 8 x 8 multiplier,

three decimation registers and a 26-bit accumulator which

can add the contents of any filter cell accumulator to the out-

put stage accumulator shifted right by eight-bits. The

HSP43481/883 has a maximum sample rate of 25.6MHz.

The effective multiply-accumulate (MAC) rate is 102MHz.

• 0MHz to 25.6MHz Sample Rate

• Four Filter Cells

• 8-Bit Coefficients and Signal Data

• Low Power CMOS Operation

- I

= 500µA Maximum

CCSB

= 110µA Maximum at 20MHz

CCOP

• 26-Bit Accumulator Per Stage

The HSP43481/883 can be configured to process expanded

coefficient and word sizes. Multiple devices can be cas-

caded for larger filter lengths without degrading the sample

rate or a single device can process larger filter lengths at

less than 25.6MHz with multiple passes. The architecture

permits processing filter lengths of over 1000 taps with the

guarantee of no overflows. In practice, most filter coefficients

are less than 1.0, making even larger filter lengths possible.

The HSP43481/883 provides for unsigned or two’s comple-

ment arithmetic, independently selectable for coefficients

and signal data.

• Filter Lengths Up To 1032 Taps

• Expandable Coefficient Size, Data Size and Filter Length

• Decimation by 2, 3 or 4

Applications

• 1-D and 2-D FIR Filters

• Radar/Sonar

• Adaptive Filters

• Echo Cancellation

• Complex Multiply-Add

• Sample Rate Converters

Each DF filter cell contains three resampling or decimation

registers which permit output sample rate reduction at rates of

/ , / or / the input sample rate. These registers also pro-

vide the capability to perform 2-D operations such as N x N

spatial correlations/convolutions for image processing appli-

cations.

Ordering Information

TEMPERA-

PART NUMBER

HSP43481GM-20/883

HSP43481GM-25/883

TURE RANGE

PACKAGE

-55^oC to +125^oC 68 Lead PGA

Block Diagram

V_CCV_SS

DIN0 - DIN7 TCS

DIENB

CIENB

DCM0 - DCM1

ERASE

TCCI

TCCO

FILTER

CELL 0

FILTER

CELL 1

FILTER

CELL 2

FILTER

CELL 3

CIN0 - CIN7

COUT0 - COUT 7

RESET

CLK

ADR0 - 1

COENB

MUX

ADR0, ADR1

RESET

CLK

OUTPUT

STAGE

SHADD

SENBL

SENBH

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.

File Number 2450.4

3-193

中文翻译

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