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HSP43481JC-25

更新时间： 2024-01-01 05:00:37
品牌 Logo 应用领域
英特矽尔 - INTERSIL 外围集成电路LTE时钟
页数 文件大小 规格书
1页 96K
描述
Digital Filter

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HSP43481JC-25 技术参数

生命周期：Contact Manufacturer包装说明：QCCJ,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.77其他特性：ICC SPECIFIED @ 20MHZ
边界扫描：NO最大时钟频率：25.6 MHz
外部数据总线宽度：8JESD-30 代码：S-PQCC-J68
低功率模式：NO端子数量：68
最高工作温度：70 °C最低工作温度：
输出数据总线宽度：26封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIER最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：J BEND
端子位置：QUADuPs/uCs/外围集成电路类型：DSP PERIPHERAL, DIGITAL FILTER
Base Number Matches：1

HSP43481JC-25 数据手册

  
®
HSP43481  
Digital Filter  
September 1997  
Features  
• Four Filter Cells  
• 0MHz to 30MHz Sample Rate  
• 8-Bit Coefficients and Signal Data  
• 26-Bit Accumulator per Stage  
• Filter Lengths Up to 1032 Tap  
Description  
The HSP43481 is a video-speed Digital Filter (DF) designed  
to efficiently implement vector operations such as FIR digital  
filters. It is comprised of four filter cells cascaded internally  
and a shift-and-add output stage, all in a single integrated  
circuit. Each filter cell contains an 8 x 8 multiplier, three dec-  
imation registers and a 26-bit accumulator which can add  
the contents of any filter cell accumulator to the output stage  
accumulator shifted right by eight-bits. The HSP43481 has a  
maximum sample rate of 30MHz. The effective multiply-  
accumulate (MAC) rate is 120MHz.  
• Expandable Coefficient Size, Data Size and Filter  
Length  
• Decimation by 2, 3 or 4  
The HSP43481 can be configured to process expanded  
coefficient and word sizes. Multiple devices can be cas-  
caded for larger filter lengths without degrading the sample  
rate or a single device can process larger filter lengths at  
less than 30MHz with multiple passes. The architecture per-  
mits processing filter lengths of over 1000 taps with the guar-  
antee of no overflows. In practice, most filter coefficients are  
less than 1.0, making even larger filter lengths possible. The  
HSP43481 provides for unsigned or two’s complement arith-  
metic, independently selectable for coefficients and signal  
data.  
Applications  
• 1-D and 2-D FIR Filters  
• Radar/Sonar  
• Adaptive Filters  
• Echo Cancellation  
• Complex Multiply-Add  
• Sample Rate Converters  
Ordering Information  
Each DF filter cell contains three resampling or decimation  
registers which permit output sample rate reduction at rates of  
1/2, 1/3 or 1/4 the input sample rate. These registers also pro-  
vide the capability to perform 2-D operations such as N x N  
spatial correlations/convolutions for image processing appli-  
cations.  
TEMPERA-  
PART NUMBER  
HSP43481JC-20  
HSP43481JC-25  
HSP43481JC-30  
HSP43481GC-20  
HSP43481GC-25  
HSP43481GC-30  
TURE RANGE  
0oC to +70oC  
0oC to +70oC  
0oC to +70oC  
0oC to +70oC  
0oC to +70oC  
0oC to +70oC  
PACKAGE  
68 Lead PLCC  
68 Lead PLCC  
68 Lead PLCC  
68 Lead PGA  
68 Lead PGA  
68 Lead PGA  
Block Diagram  
V
V
SS  
CC  
DIN0 - DIN7 TCS  
DIENB  
CIENB  
8
5
DCM0 - DCM1  
ERASE  
8
8
8
8
TCCI  
TCCO  
FILTER  
CELL 0  
FILTER  
CELL 1  
FILTER  
CELL 2  
FILTER  
CELL 3  
8
4
8
8
8
8
CIN0 - CIN7  
COUT0 - COUT 7  
RESET  
CLK  
26  
26  
26  
4
26  
COENB  
2
ADR0 - 1  
MUX  
26  
ADR0, ADR1  
2
RESET  
CLK  
SHADD  
OUTPUT  
STAGE  
SENBL  
2
SENBH  
26  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
File Number 2759.4  
Copyright © Intersil Americas Inc. 2002. All Rights Reserved  
3-1  
1

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