Datasheet > HSP43881GC-30

HSP43881GC-30

更新时间： 2024-11-13 22:09:47

品牌	Logo	应用领域
英特矽尔 - INTERSIL		外围集成电路 LTE 时钟
页数	文件大小	规格书
21页	151K
描述
Digital Filter

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HSP43881GC-30 数据手册

HSP43881

Data Sheet

May 1999

File Number 2758.4

Digital Filter

Features

The HSP43881 is a video speed Digital Filter (DF) designed

to efﬁciently implement vector operations such as FIR digital

ﬁlters. It is comprised of eight ﬁlter cells cascaded internally

and a shift and add output stage, all in a single integrated

circuit. Each ﬁlter cell contains a 8 x 8-bit multiplier, three

decimation registers and a 26-bit accumulator. The output

stage contains an additional 26-bit accumulator which can

add the contents of any ﬁlter cell accumulator to the output

stage accumulator shifted right by 8 bits. The HSP43881 has

a maximum sample rate of 30MHz. The effective multiply

accumulate (mac) rate is 240MHz.

• Eight Filter Cells

• 0MHz to 30MHz Sample Rate

• 8-Bit Coefﬁcients and Signal Data

• 26-Bit Accumulator Per Stage

• Filter Lengths Over 1000 Taps

• Expandable Coefﬁcient Size, Data Size and Filter Length

• Decimation by 2, 3 or 4

Applications

The HSP43881 DF can be conﬁgured to process expanded

coefﬁcient and word sizes. Multiple DFs can be cascaded for

larger ﬁlter lengths without degrading the sample rate or a

single DF can process larger ﬁlter lengths at less than

30MHz with multiple passes. The architecture permits

processing ﬁlter lengths of over 1000 taps with the

guarantee of no overﬂows. In practice, most ﬁlter coefﬁcients

are less than 1.0, making even larger ﬁlter lengths possible.

The DF provides for 8-bit unsigned or two’s complement

arithmetic, independently selectable for coefﬁcients and

signal data.

• 1-D and 2-D FIR Filters

• Radar/Sonar

• Adaptive Filters

• Echo Cancellation

• Complex Multiply-Add

• Sample Rate Converters

Ordering Information

PART

NUMBER

TEMP. RANGE

( C)

PACKAGE

84 Ld PLCC

85 Ld PGA

PKG. NO.

N84.1.15

G85.A

Each DF ﬁlter cell contains three resampling or decimation

registers which permit output sample rate reduction at rates

HSP43881JC-20

HSP43881JC-25

HSP43881JC-30

HSP43881GC-20

HSP43881GC-25

HSP43881GC-30

0 to 70

of / , / or / the input sample rate. These registers also

provide the capability to perform 2-D operations such as

matrix multiplication and N x N spatial

correlations/convolutions for image processing applications.

G85.A

Block Diagram

DIN0 - DIN7 TCS

DIENB

CIENB

DCMO - 1

ERASE

TCCI

TCCO

FILTER

CELL 0

FILTER

CELL 1

FILTER

CELL 2

FILTER

CELL 3

FILTER

CELL 4

FILTER

CELL 5

FILTER

CELL 6

FILTER

CELL 7

CIN0 - 7

COUT0 - 7

RESET

CLK

COENB

ADR0 - 2

MUX

RESET

CLK

ADR0, ADR1, ADR2

OUTPUT

STAGE

SHADD

SENBL

SENBH

SUM0 - 25

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

12 3 4 5 6 7...21

中文翻译

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与HSP43881GC-30相关器件

型号	品牌	获取价格	描述	数据表
HSP43881GM-20/883	RENESAS	获取价格	IC,DIGITAL FILTER,CMOS,PGA,84PIN,CERAMIC
HSP43881GM-25/883	INTERSIL	获取价格	Digital Filter
HSP43881JC-20	INTERSIL	获取价格	Digital Filter
HSP43881JC-25	INTERSIL	获取价格	Digital Filter
HSP43881JC-30	INTERSIL	获取价格	Digital Filter
HSP43881QM-20/883	ETC	获取价格	Digital Filter
HSP43881QM-25/883	ETC	获取价格	Digital Filter
HSP43891	INTERSIL	获取价格	Digital Filter
HSP43891/883	INTERSIL	获取价格	Digital Filter
HSP43891883	INTERSIL	获取价格	Digital Filter

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