Datasheet > HSP43891GM-25/883

HSP43891GM-25/883

更新时间： 2024-09-20 22:09:47

品牌	Logo	应用领域
英特矽尔 - INTERSIL		外围集成电路 LTE 时钟
页数	文件大小	规格书
7页	154K
描述
Digital Filter

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HSP43891GM-25/883 数据手册

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HSP43891/883

Data Sheet

May 1999

FN2451.4

Digital Filter

Features

The HSP43891/883 is a video-speed Digital Filter (DF)

designed to efficiently implement vector operations such as

FIR digital filters. It is comprised of eight filter cells cascaded

internally and a shift and add output stage, all in a single

integrated circuit. Each filter cell contains a 9 x 9 two’s

complement multiplier, three decimation registers and a 26-

bit accumulator. The output stage contains an additional 26-

bit accumulator which can add the contents of any filter cell

accumulator to the output stage accumulator shifted right by

8-bits. The HSP43891/883 has a maximum sample rate of

25.6MHz. The effective multiply-accumulate (mac) rate is

204MHz.

• This Circuit is Processed in Accordance to MIL-STD-883

and is Fully Conformant Under the Provisions of

Paragraph 1.2.1.

• 0MHz to 25.6MHz Sample Rate

• Eight Filter Cells

• 9-Bit Coefficients and Signal Data

• Low Power CMOS Operation

- ICCSB = 500µA Maximum

- ICCOP = 160µA Maximum at 20MHz

• 26-Bit Accumulator per Stage

• Filter Lengths Up to 1032 Taps

The HSP43891/883 DF can be configured to process

expanded coefficient and word sizes. Multiple DFs can be

cascaded for larger filter lengths without degrading the

sample rate or a single DF can process larger filter lengths

at less than 25.6MHz with multiple passes. The architecture

permits processing filter lengths of over 1000 taps with the

guarantee of no overflows. In practice, most filter coefficients

are less than 1.0, making even larger filter lengths possible.

The DF provides for 8-bit unsigned or 9-bit two’s

• Expandable Coefficient Size, Data Size and Filter Length

• Decimation by 2, 3 or 4

Applications

• 1-D and 2-D FIR Filters

• Radar/Sonar

• Digital Video

complement arithmetic, independently selectable for

coefficients and signal data.

• Adaptive Filters

• Echo Cancellation

• Complex Multiply-Add

• Sample Rate Converter

Ordering Information

Each DF filter cell contains three re-sampling or decimation

registers which permit output sample rate reduction at rates

of / , / or / the input sample rate. These registers also

provide the capability to perform 2-D operations such as

matrix multiplication and N x N spatial

correlations/convolutions for image processing applications.

TEMP.

RANGE ( C)

PKG.

NO.

PART NUMBER

HSP43891GM-20/883

HSP43891GM-25/883

PACKAGE

-55 to 125 85 Ld PGA

G85.A

Block Diagram

DIN0 - DIN8

DIENB

CIENB

DCM0 - 1

ERASE

FILTER

CELL 0

FILTER

CELL 1

FILTER

CELL 2

FILTER

CELL 3

FILTER

CELL 4

FILTER

CELL 5

FILTER

CELL 6

FILTER

CELL 7

CIN0 - 8

COUT0 - 8

COENB

RESET

CLK

ADR0 - 2

MUX

RESET

CLK

ADR0, ADR1, ADR2

OUTPUT

STAGE

SHADD

SENBL

SENBH

SUM0 - 25

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.

12 3 4 5 6 7

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