HSP43891
Data Sheet
May 1999
File Number 2785.5
Digital Filter
Features
The HSP43891 is a video-speed Digital Filter (DF)
designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of eight filter cells
cascaded internally and a shift and add output stage, all in
a single integrated circuit. Each filter cell contains a 9x9
two’s complement multiplier, three decimation registers and
a 26-bit accumulator. The output stage contains an
additional 26-bit accumulator which can add the contents of
any filter cell accumulator to the output stage accumulator
shifted right by 8-bits. The HSP43891 has a maximum
sample rate of 30MHz. The effective multiply-accumulate
(mac) rate is 240MHz.
• Eight Filter Cells
• 0MHz to 30MHz Sample Rate
• 9-Bit Coefficients and Signal Data
• 26-Bit Accumulator per Stage
• Filter Lengths Over 1000 Taps
• Expandable Coefficient Size, Data Size and Filter Length
• Decimation by 2, 3 or 4
Applications
• 1-D and 2-D FIR Filters
• Radar/Sonar
The HSP43891 DF can be configured to process expanded
coefficient and word sizes. Multiple DFs can be cascaded
for larger filter lengths without degrading the sample rate or
a single DF can process larger filter lengths at less than
30MHz with multiple passes. The architecture permits
processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter
coefficients are less than 1.0, making even larger filter
lengths possible. The DF provides for 8-bit unsigned or
9-bit two’s complement arithmetic, independently
selectable for coefficients and signal data.
• Digital Video
• Adaptive Filters
• Echo Cancellation
• Complex Multiply-Add
- Sample Rate Converters
Ordering Information
TEMP.
o
PART NUMBER RANGE ( C)
PACKAGE
PKG. NO.
HSP43891VC-20
HSP43891VC-25
HSP43891VC-30
HSP43891JC-20
HSP43891JC-25
HSP43891JC-30
HSP43891GC-20
HSP43891GC-25
HSP43891GC-30
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
100 Lead MQFP Q100.14x20
100 Lead MQFP Q100.14x20
100 Lead MQFP Q100.14x20
84 Lead PLCC N84.1.15
84 Lead PLCC N84.1.15
84 Lead PLCC N84.1.15
85 Pin CPGA G85.A
Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates
1
1
1
of / , / or / the input sample rate. These registers also
2
3
4
provide the capability to perform 2-D operations such as
matrix multiplication and NxN spatial
correlations/convolutions for image processing applications.
85 Pin CPGA G85.A
85 Pin CPGA G85.A
Block Diagram
V
V
DIN0 - DIN8
9
CC
SS
DIENB
CIENB
5
DCM0 - 1
ERASE
DF
FILTER
CELL 0
DF
FILTER
CELL 1
DF
FILTER
CELL 2
DF
FILTER
CELL 3
DF
FILTER
CELL 4
DF
FILTER
CELL 5
DF
FILTER
CELL 6
DF
FILTER
CELL 7
9
9
9
9
9
9
9
9
9
CIN0 - 8
COUT0 - 8
COENB
RESET
CLK
ADRO - 2
26
26
26
26
26
26
26
5
5
26
3
MUX
26
RESET
CLK
ADR0, ADR1, ADR2
2
OUTPUT
STAGE
SHADD
SENBL
SENBH
2
26
SUM0 - 25
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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