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HSP43881

更新时间: 2024-11-13 22:48:31
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英特矽尔 - INTERSIL /
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21页 151K
描述
Digital Filter

HSP43881 数据手册

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HSP43881  
Data Sheet  
May 1999  
File Number 2758.4  
Digital Filter  
Features  
The HSP43881 is a video speed Digital Filter (DF) designed  
to efficiently implement vector operations such as FIR digital  
filters. It is comprised of eight filter cells cascaded internally  
and a shift and add output stage, all in a single integrated  
circuit. Each filter cell contains a 8 x 8-bit multiplier, three  
decimation registers and a 26-bit accumulator. The output  
stage contains an additional 26-bit accumulator which can  
add the contents of any filter cell accumulator to the output  
stage accumulator shifted right by 8 bits. The HSP43881 has  
a maximum sample rate of 30MHz. The effective multiply  
accumulate (mac) rate is 240MHz.  
• Eight Filter Cells  
• 0MHz to 30MHz Sample Rate  
• 8-Bit Coefficients and Signal Data  
• 26-Bit Accumulator Per Stage  
• Filter Lengths Over 1000 Taps  
• Expandable Coefficient Size, Data Size and Filter Length  
• Decimation by 2, 3 or 4  
Applications  
The HSP43881 DF can be configured to process expanded  
coefficient and word sizes. Multiple DFs can be cascaded for  
larger filter lengths without degrading the sample rate or a  
single DF can process larger filter lengths at less than  
30MHz with multiple passes. The architecture permits  
processing filter lengths of over 1000 taps with the  
guarantee of no overflows. In practice, most filter coefficients  
are less than 1.0, making even larger filter lengths possible.  
The DF provides for 8-bit unsigned or two’s complement  
arithmetic, independently selectable for coefficients and  
signal data.  
• 1-D and 2-D FIR Filters  
• Radar/Sonar  
• Adaptive Filters  
• Echo Cancellation  
• Complex Multiply-Add  
• Sample Rate Converters  
Ordering Information  
PART  
NUMBER  
TEMP. RANGE  
o
( C)  
PACKAGE  
84 Ld PLCC  
84 Ld PLCC  
84 Ld PLCC  
85 Ld PGA  
85 Ld PGA  
85 Ld PGA  
PKG. NO.  
N84.1.15  
N84.1.15  
N84.1.15  
G85.A  
Each DF filter cell contains three resampling or decimation  
registers which permit output sample rate reduction at rates  
HSP43881JC-20  
HSP43881JC-25  
HSP43881JC-30  
HSP43881GC-20  
HSP43881GC-25  
HSP43881GC-30  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
1
1
1
of / , / or / the input sample rate. These registers also  
2
3
4
provide the capability to perform 2-D operations such as  
matrix multiplication and N x N spatial  
correlations/convolutions for image processing applications.  
G85.A  
G85.A  
Block Diagram  
V
V
SS  
CC  
DIN0 - DIN7 TCS  
8
DIENB  
CIENB  
5
DCMO - 1  
ERASE  
8
8
8
8
8
8
8
8
TCCI  
TCCO  
DF  
DF  
DF  
DF  
DF  
DF  
DF  
DF  
FILTER  
CELL 0  
FILTER  
CELL 1  
FILTER  
CELL 2  
FILTER  
CELL 3  
FILTER  
CELL 4  
FILTER  
CELL 5  
FILTER  
CELL 6  
FILTER  
CELL 7  
8
5
8
8
8
8
8
8
8
8
CIN0 - 7  
COUT0 - 7  
RESET  
CLK  
26  
26  
26  
26  
26  
26  
26  
5
26  
COENB  
3
ADR0 - 2  
MUX  
26  
RESET  
CLK  
ADR0, ADR1, ADR2  
2
OUTPUT  
STAGE  
SHADD  
SENBL  
SENBH  
2
26  
SUM0 - 25  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
1

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