®
HSP43481
Digital Filter
September 1997
Features
• Four Filter Cells
• 0MHz to 30MHz Sample Rate
• 8-Bit Coefficients and Signal Data
• 26-Bit Accumulator per Stage
• Filter Lengths Up to 1032 Tap
Description
The HSP43481 is a video-speed Digital Filter (DF) designed
to efficiently implement vector operations such as FIR digital
filters. It is comprised of four filter cells cascaded internally
and a shift-and-add output stage, all in a single integrated
circuit. Each filter cell contains an 8 x 8 multiplier, three dec-
imation registers and a 26-bit accumulator which can add
the contents of any filter cell accumulator to the output stage
accumulator shifted right by eight-bits. The HSP43481 has a
maximum sample rate of 30MHz. The effective multiply-
accumulate (MAC) rate is 120MHz.
• Expandable Coefficient Size, Data Size and Filter
Length
• Decimation by 2, 3 or 4
The HSP43481 can be configured to process expanded
coefficient and word sizes. Multiple devices can be cas-
caded for larger filter lengths without degrading the sample
rate or a single device can process larger filter lengths at
less than 30MHz with multiple passes. The architecture per-
mits processing filter lengths of over 1000 taps with the guar-
antee of no overflows. In practice, most filter coefficients are
less than 1.0, making even larger filter lengths possible. The
HSP43481 provides for unsigned or two’s complement arith-
metic, independently selectable for coefficients and signal
data.
Applications
• 1-D and 2-D FIR Filters
• Radar/Sonar
• Adaptive Filters
• Echo Cancellation
• Complex Multiply-Add
• Sample Rate Converters
Ordering Information
Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates of
1/2, 1/3 or 1/4 the input sample rate. These registers also pro-
vide the capability to perform 2-D operations such as N x N
spatial correlations/convolutions for image processing appli-
cations.
TEMPERA-
PART NUMBER
HSP43481JC-20
HSP43481JC-25
HSP43481JC-30
HSP43481GC-20
HSP43481GC-25
HSP43481GC-30
TURE RANGE
0oC to +70oC
0oC to +70oC
0oC to +70oC
0oC to +70oC
0oC to +70oC
0oC to +70oC
PACKAGE
68 Lead PLCC
68 Lead PLCC
68 Lead PLCC
68 Lead PGA
68 Lead PGA
68 Lead PGA
Block Diagram
V
V
SS
CC
DIN0 - DIN7 TCS
DIENB
CIENB
8
5
DCM0 - DCM1
ERASE
8
8
8
8
TCCI
TCCO
FILTER
CELL 0
FILTER
CELL 1
FILTER
CELL 2
FILTER
CELL 3
8
4
8
8
8
8
CIN0 - CIN7
COUT0 - COUT 7
RESET
CLK
26
26
26
4
26
COENB
2
ADR0 - 1
MUX
26
ADR0, ADR1
2
RESET
CLK
SHADD
OUTPUT
STAGE
SENBL
2
SENBH
26
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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