Datasheet > GD16543-40AB

GD16543-40AB

更新时间： 2024-11-11 23:53:39

品牌	Logo	应用领域
其他 - ETC		时钟
页数	文件大小	规格书
9页	134K
描述
CLOCK/DATA RECOVERY\|QFL\|40PIN\|CERAMIC

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中文翻译

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数据手册

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GD16543-40AB 数据手册

2.5 Gbit/s

Clock and Data

Recovery Circuit

GD16543

an Intel company

Preliminary

General Description

Features

The GD16543 is a high performance

monolithic integrated Clock and Data Re-

covery (CDR) device applicable for opti-

cal communication systems including:

The device meets all ITU-T jitter require-

ments when used with the recommended

loop filter (jitter tolerance, -transfer and

-generation).

Clock and Data Recovery covering

2.3 Gbit/s to 2.7 Gbit/s.

SDH STM-16, SONET OC-48

compatible.

SDH STM-16

SONET OC-48

The integrated 1:4 demultiplexer with dif-

ferential ECL outputs ensures a simple

and universal interface to the system

CMOS ASICs.

Differential Data inputs with 20 mV

sensitivity.

The CDR contains all circuits needed for

reliable acquisition and lock of the VCO

phase to the incoming data-stream.

Differential ECL Data and Clock

outputs.

The 622 MHz output clock is maintained

within 500 ppm tolerance even in ab-

sence of data.

The electrical input sensitivity is better

than 20 mV. Optical receivers with sensi-

tivity better than -34 dBm have been ob-

tained without optical pre-amplifiers.

Acquisition time: < 500 ms

The GD16543 is available in a 40 lead

ceramic LCC and in a 48 lead 7x7 mm

TQFP power enhanced plastic package.

Few external passive components

needed.

50 W Loop-Through data inputs for

higher sensitivity.

Single supply operation.

Power dissipation: 1 W.

Limiter

DOUT0

DOUN0

SIPO

Available in:

–

Bang

SIPI

SINI

DOUT1

DOUN1

a 48 lead 7x7 mm TQFP plastic

package

a 40 lead ceramic LCC.

De-

MUX

Phase

Detector

DOUT2

DOUN2

–

SINO

DOUT3

DOUN3

CKOUT

CKOUN

REFXI

Phase

Frequency

Detector

Applications

REFXO

VDD

Change

Pump

Clock and Data Recovery for optical

communication systems including:

VCO

VEE

VDDA

VEEA

–

SDH STM-16

SONET OC-48

Lock

SEL1

SEL2

Detect

RES

LOCK

CHPO

VCTL

Data Sheet Rev.: 07

12 3 4 5 6 7...9

中文翻译

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