Datasheet > EDI2CG472256V-D2

EDI2CG472256V-D2

更新时间： 2024-09-19 23:50:03

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
12页	370K
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SSRAM Modules

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EDI2CG472256V-D2 数据手册

EDI2CG472256V

4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through

FEATURES

■ 4x256Kx72 Synchronous, Synchronous Burst

■ Flow-Through Architecture

The EDI2CG472256VxxD2 is a Synchronous/Synchronous Burst

SRAM, 84 position Dual Key; Double High DIMM (168 contacts)

Module, organized as 4x256Kx72. The Module contains sixteen

(16) Synchronous Burst Ram Devices, packaged in the industry

standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4

Substrate. The module architecture is defined as a Sync/Sync

Burst, Flow-Through, with support for either linear or sequential

burst. This module provides High Performance, 2-1-1-1 accesses

when used in Burst Mode, and used as a Synchronous Only Mode,

provides a high performance cost advantage over BiCMOS

aysnchronous device architectures.

■ Linear and Sequential Burst Support via MODE pin

■ Clock Controlled Registered Module Enable (EM\)

■ Clock Controlled Registered Bank Enables (E1\, E2\, E3\, E4\)

■ Clock Controlled Byte Write Mode Enable (BWE\)

■ Clock Controlled Byte Write Enables (BW1\ - BW8\)

■ Clock Controlled Registered Address

■ Clock Controlled Registered Global Write (GW\)

■ Aysnchronous Output Enable (G\)

Synchronous Only operations are performed via strapping ADSC\

Low, and ADSP\ / ADV\ High, which provides for Ultra Fast

Accesses in Read Mode while providing for internally self-timed

Early Writes.

■ Internally self-timed Write

■ Individual Bank Sleep Mode enables (ZZ1, ZZ2, ZZ3, ZZ4)

■ Gold Lead Finish

■ 3.3V ±10%, - 5% Operation

Synchronous/Synchronous Burst operations are in relation to an

externally supplied clock, Registered Address, Registered Global

Write, Registered Enables as well as an Asynchronous Output

enable. This Module has been defined with full flexibility, which

allows individual control of each of the eight bytes, as well as

Quad Words in both Read and Write Operations.

■ Access Speed(s): tKHQV = 9, 10, 12, 15ns

■ Common Data I/O

■ High Capacitance (30pF) drive, at rated Access Speed

■ Single total array Clock

■ Multiple Vcc and Gnd

White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com

August 1998 Rev. 1

ECO #10656

12 3 4 5 6 7...12

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