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EDI2DL32256V35BC PDF预览

EDI2DL32256V35BC

更新时间: 2024-11-08 03:33:27
品牌 Logo 应用领域
WEDC 存储内存集成电路静态存储器
页数 文件大小 规格书
8页 98K
描述
256Kx32 Synchronous Pipline Burst SRAM 3.3V

EDI2DL32256V35BC 数据手册

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EDI2DL32256V  
256Kx32 Synchronous Pipline Burst SRAM 3.3V  
FEATURES  
DESCRIPTION  
tKHQV times of 3.5, 3.8 and 4.0ns  
166, 150 and 133 MHz clock speed  
DSP Memory Solution  
The EDI2DL32256VxxBC is a 3.3V, 256Kx32 Synchronous Pipeline  
Burst SRAM constructed with two 256Kx16 die mounted on a  
multi-layer laminate substrate. The device is packaged in a 119  
lead,14mmby22mm,BGA.It is available withclockspeeds of166,  
150 and 133 MHz. The device is a Pipeline Burst SRAM, allowing  
the user to develop a fast external memory for Texas Instruments’  
C6x”. In Burst Mode data from the first memory location is  
available in three clock cycles, while the subsequent data is  
available in one clock cycle (3/1/1/1). Subsequent burst ad-  
dresses are generated by the TMS320C6x DSP. Individual address  
locations can also be read, allowing one memory access in 3 clock  
cycles. Allsynchronous inputs are gatedbyregisters controlledby  
a positive-edge-triggered clock input (CLK). The synchronous in-  
puts include all addresses, all data inputs, chip enable (CE\), burst  
control input (ADSC\), byte write enables (BW0\ to BW3\) and  
Write Enable (BWE\).  
Texas Instruments’ TMS320C6201  
Texas Instruments’ TMS320C67x  
Package:  
• 119 pin BGA, JEDEC MO-163  
3.3V Operating Supply Voltage  
3.5ns Output Enable access time  
Single Write Control and Output Enable Lines  
Single Chip Enable Line  
56% space savings vs. monolithic TQFPs  
Multiple VCC and VSS pins  
Asynchronous inputs include the output enable (OE\), burst mode  
control (MODE), and sleep mode control (ZZ). The data outputs  
(DQ), enabled by OE\, are also asynchronous.  
Reduced inductance and capacitance  
Address lines and the chip enable are registered with the address  
status controller (ADSC\) input pin.  
FIG. 1  
PIN CONFIGURATION  
BLOCK DIAGRAM  
1
2
3
4
NC  
ADSC\  
VDD  
NC  
CE\  
OE\  
NC  
NC  
VDD  
CLK  
NC  
BWE\  
A1  
5
6
7
A
B
C
D
E
F
VDD  
NC  
A
A
A
A
VDD  
NC  
A
B
C
D
E
F
A0-17  
CLK  
NC  
A
A
A
NC  
A
A
A
A
NC  
ADSC\  
OE\  
BWE\  
CE\  
MODE  
ZZ  
DQ16  
DQ18  
VDD  
DQ21  
DQ23  
VDD  
DQ31  
DQ29  
VDD  
DQ26  
DQ24  
NC  
NC  
VSS  
VSS  
VSS  
BE2\  
VSS  
NC  
VSS  
BE3\  
VSS  
VSS  
VSS  
MODE  
A
VSS  
VSS  
VSS  
BE1\  
VSS  
NC  
VSS  
BE0\  
VSS  
VSS  
VSS  
NC  
A
NC  
DQ9  
DQ11  
DQ12  
DQ14  
VDD  
DQ6  
DQ4  
DQ3  
DQ1  
NC  
A
DQ8  
DQ10  
VDD  
DQ13  
DQ15  
VDD  
DQ7  
DQ5  
VDD  
DQ2  
DQ0  
NC  
256K X 16  
SSRAM  
DQ17  
DQ19  
DQ20  
DQ22  
VDD  
DQ30  
DQ28  
DQ27  
DQ25  
NC  
BE  
BE  
0
1
\
\
G
H
J
G
H
J
BE  
BE  
2
3
\
\
DQ  
DQ  
DQ16  
0
8
-
-
7
15  
K
L
M
N
P
K
L
M
N
P
-
-
23  
31  
256K X 16  
SSRAM  
DQ24  
A0  
R
T
U
A
VDD  
A
R
T
U
NC  
NC  
NC  
NC  
6
ZZ  
VDD  
1
NC  
NC  
3
NC  
4
NC  
5
VDD  
7
2
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com  
November 2000, Rev. 1  
ECO #13417  

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