5秒后页面跳转
EDI2GG418128V12D PDF预览

EDI2GG418128V12D

更新时间: 2024-09-20 19:56:47
品牌 Logo 应用领域
WEDC 静态存储器内存集成电路
页数 文件大小 规格书
8页 218K
描述
SRAM Card, 512KX18, 12ns, CMOS, CARD EDGE, DIMM-120

EDI2GG418128V12D 数据手册

 浏览型号EDI2GG418128V12D的Datasheet PDF文件第2页浏览型号EDI2GG418128V12D的Datasheet PDF文件第3页浏览型号EDI2GG418128V12D的Datasheet PDF文件第4页浏览型号EDI2GG418128V12D的Datasheet PDF文件第5页浏览型号EDI2GG418128V12D的Datasheet PDF文件第6页浏览型号EDI2GG418128V12D的Datasheet PDF文件第7页 
EDI2GG418128V  
4x128Kx18, 3.3V Synchronous Flow-Through SRAM CARD EDGE DIMM  
FEATURES  
4x128Kx18 Synchronous  
The EDI2GG418128VxxD2 is a Synchronous SRAM, 60 position  
Card Edge; DIMM (120 contacts) module, organized as 4x128Kx64.  
The module contains four (4) Synchronous Burst Ram Devices,  
packaged in the industry standard JEDEC 14mmx20mm TQFP  
placed on a Multilayer FR4 Substrate. The module architecture is  
defined as a Synchronous Only, Flow-Through, Early Write De-  
vice. This module provides high performance, ultra fast access  
times at a cost per bit benefit over BiCMOS Asynchronous SRAM  
based Devices. As well as improved cost per bit, the use of  
synchronous, or synchronous Burst devices or modules can ease  
the memory subsystem design by reducing or easing the memory  
controller requirement.  
Access Speed(s): TKHQV = 9.5, 10, 11, 12, 15ns  
Flow-Through Architecture  
Clock Controlled Registered Bank Enables (E1\, E2\,E3\,E4\)  
Clock Controlled Registered Address  
Clock Controlled Registered Global Write (GW\)  
Aysnchronous Output Enable (G\)  
Internally self-timed Write  
Gold Lead Finish  
3.3V ±10%, -5% Operation  
Synchronous operations are in relation to an externally supplied  
clock, registered address, registered global write, registered  
enables as well as an Asynchronous Output enable. All read and  
write operations to this module are performed on long words  
(double words) 32 bit operation.  
Common Data I/O  
High Capacitance (30pF) drive, at rated Access Speed  
Single total array Clock  
Multiple Vcc and Vss  
Write cycles are internally self timed and are initiated by a rising  
clock edge. This feature relieves the designer the task of devel-  
oping external write pulse width circuitry.  
1
January 1999 Rev. 0  
ECO# 10857  
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com  

与EDI2GG418128V12D相关器件

型号 品牌 获取价格 描述 数据表
EDI2GG418128V15D WEDC

获取价格

SRAM Card, 512KX18, 15ns, CMOS, CARD EDGE, DIMM-120
EDI2GG418128V95D WEDC

获取价格

SRAM Card, 512KX18, 9.5ns, CMOS, CARD EDGE, DIMM-120
EDI2GG41864V10D WEDC

获取价格

SRAM Card, 256KX18, 10ns, CMOS, CARD EDGE, DIMM-120
EDI2GG41864V11D WEDC

获取价格

SRAM Card, 256KX18, 11ns, CMOS, CARD EDGE, DIMM-120
EDI2GG41864V15D WEDC

获取价格

SRAM Card, 256KX18, 15ns, CMOS, CARD EDGE, DIMM-120
EDI2GG432128V10D WEDC

获取价格

SRAM Card, 512KX32, 10ns, CMOS, CARD EDGE, DIMM-120
EDI2GG432128V12D WEDC

获取价格

SRAM Card, 512KX32, 12ns, CMOS, CARD EDGE, DIMM-120
EDI2GG464128V WEDC

获取价格

4MB SYNCHRONOUS CARD EDGE DIMM
EDI2GG464128V10D WEDC

获取价格

4MB SYNCHRONOUS CARD EDGE DIMM
EDI2GG464128V11D WEDC

获取价格

4MB SYNCHRONOUS CARD EDGE DIMM