Datasheet > EDI2GG46464V10D

EDI2GG46464V10D

更新时间： 2024-11-08 15:31:31

品牌	Logo	应用领域
WEDC		静态存储器内存集成电路
页数	文件大小	规格书
8页	247K
描述
SRAM Card, 256KX64, 10ns, CMOS, CARD EDGE, DIMM-120

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EDI2GG46464V10D 数据手册

EDI2GG46464V

4x64Kx64, 3.3V Synchronous SRAM CARD EDGE DIMM

FEATURES

■ 4x64Kx64 Synchronous

The EDI2GG46464VxxD is a Synchronous SRAM, 60 position

Dual Key; Card Edge DIMM (120 contacts) Module, organized as

4x64Kx64. The Module contains eight (8) Synchronous Burst

RamDevices,packagedintheindustrystandardJEDEC14mmx20mm

TQFPplacedonaMultilayerFR4Substrate. Themodulearchitecture

is defined as a Synchronous Only, Flow-Through, Early Write

device. This Module provides high performance, ultra fast access

times at a cost per bit benefit over BiCMOS Asynchronous devices.

As well as improved cost per bit, the use of Synchronous or

Synchronous burst devices or modules can ease the memory

subsystem design by reducing or easing the memory controller

requirement.

■ Access Speed(s): TKHQV = 9.5, 10, 11,12, 15ns

■ Flow-Through Architecture

■ Clock Controlled Registered Bank Enables (E1\,E2\, E3\, E4\)

■ Clock Controlled Registered Address

■ Clock Controlled Registered Global Write (GW\)

■ Aysnchronous Output Enable (G\)

■ Internally self-timed Write+

■ Gold Lead Finish

■ 3.3V ±10%, -5% Operation

Synchronous operations are in relation to an externally supplied

clock, registeredaddress, registeredglobalwrite, registeredenables

as well as an Asynchronous Output enable. All Read and Write

operations are performed in Quad Words (64 bit operations).

■ Common Data I/O

■ High Capacitance (30pF) drive, at rated Access Speed

■ Single total array Clock

Write cycles are internally self timed and are initiated by a rising

clock edge. This feature relieves the designer the task of developing

external pulse width circuitry.

■ Multiple Vcc and Vss

White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com

February 1999 Rev. 2

ECO# 10858

12 3 4 5 6 7 8

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