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EDI2GG464128V15D PDF预览

EDI2GG464128V15D

更新时间: 2024-11-08 03:43:23
品牌 Logo 应用领域
WEDC /
页数 文件大小 规格书
8页 249K
描述
4MB SYNCHRONOUS CARD EDGE DIMM

EDI2GG464128V15D 数据手册

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EDI2GG464128V  
White Electronic Designs  
4MB SYNCHRONOUS CARD EDGE DIMM  
FEATURES  
DESCRIPTION  
4x128Kx64 Synchronous  
The EDI2KG64128VxxD is a Synchronous SRAM,  
60 position Card Edge DIMM (120 contacts) Module,  
organized as 4x128Kx64. The Module contains eight  
(8) Synchronous Burst Ram Devices, packaged in the  
industry standard JEDEC 14mmx20mm TQFP placed on  
a Multilayer FR4 Substrate. The module architecture is  
defined as a Synchronous Only, Flow-Through, Early Write  
Device. This module provides High Performance, Ultra  
Fast access times at a cost per bit benefit over BiCMOS  
Asynchronous SRAM based devices. As well as improved  
cost per bit, the use of Synchronous or Synchronous Burst  
devices or modules can ease the memory subsystem  
design by reducing or easing the memory controller  
requirement.  
Access Speed(s): TKHQV = 9.5, 10, 11, 12, 15ns  
Flow-Through Architecture  
Clock Controlled Registered Bank Enables (E1#,  
E2#, E3#, E4#)  
Clock Controlled Registered Address  
Clock Controlled Registered Global Write (GW#)  
Aysnchronous Output Enable (G#)  
Internally self-timed Write  
Gold Lead Finish  
3.3V +10%, -5% Operation  
Access Speed(s): tKHQV = 9.5, 10, 11, 12, 15ns  
Common Data I/O  
Synchronous operations are in relation to an externally  
supplied clock, Registered Address, Registered Global  
Write, Registered Enables as well as an Asynchronous  
Output enable. All read and write operations to this module  
are performed on Quad Words (64 bit operations).  
High Capacitance (30pf) drive, at rated Access  
Speed  
Single total array Clock  
Multiple Vcc and GND  
Write cycles are internally self timed and are initiated by  
a rising clock edge. This feature relieves the designer the  
task of developing external write pulse width circuitry.  
*This product is subject to change without notice.  
PIN NAMES  
DQ0-DQ63  
A015  
Input/Output Bus  
Address Bus  
E1#, E2#,  
E3#, E4#  
Synchronous Bank Enables  
CK  
Array Clock  
GW#  
G#  
Synchronous Global Write Enable  
Asynchronous Output Enable  
3.3V Power Supply  
Ground  
Vcc  
Vss  
NC  
No Connect  
October 2004  
Rev. 1  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  

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