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DSP56307 PDF预览

DSP56307

更新时间: 2024-02-24 05:34:41
品牌 Logo 应用领域
飞思卡尔 - FREESCALE 数字信号处理器
页数 文件大小 规格书
64页 1130K
描述
24-BIT DIGITAL SIGNAL PROCESSOR

DSP56307 技术参数

生命周期:Obsolete包装说明:PLASTIC, BGA-196
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.84
其他特性:ALSO REQUIRES 3.3V SUPPLY地址总线宽度:18
桶式移位器:YES边界扫描:YES
最大时钟频率:100 MHz外部数据总线宽度:24
格式:FIXED POINT内部总线架构:MULTIPLE
JESD-30 代码:S-PBGA-B196长度:17 mm
低功率模式:NO端子数量:196
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
认证状态:Not Qualified座面最大高度:1.75 mm
标称供电电压:2.5 V表面贴装:YES
技术:CMOS端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
宽度:17 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

DSP56307 数据手册

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DSP56374  
Rev. 4.2, 1/2007  
Freescale Semiconductor  
Data Sheet: Technical Data  
DSP56374 Data Sheet  
Table of Contents  
1 Overview  
The DSP56374 is a high-density CMOS device with  
3.3 V inputs and outputs.  
1
2
3
4
5
6
7
8
9
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 25  
Power Requirements . . . . . . . . . . . . . . . . . . . . . 26  
Thermal Characteristics . . . . . . . . . . . . . . . . . . . 27  
DC Electrical Characteristics . . . . . . . . . . . . . . . 28  
AC Electrical Characteristics. . . . . . . . . . . . . . . . 29  
NOTE  
This document contains information on a  
new product. Specifications and  
information herein are subject to change  
without notice.  
10 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
11 External Clock Operation . . . . . . . . . . . . . . . . . . 29  
12 Reset, Stop, Mode Select, and Interrupt Timing. 32  
13 Serial Host Interface SPI Protocol Timing. . . . . . 35  
14 Serial Host Interface (SHI) I2C Protocol Timing . 41  
15 Programming the Serial Clock . . . . . . . . . . . . . . 43  
16 Enhanced Serial Audio Interface Timing. . . . . . . 44  
17 Timer Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
18 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
19 JTAG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
20 Watchdog Timer Timing . . . . . . . . . . . . . . . . . . . 53  
For software or simulation models (for  
example, IBIS files), contact sales or go  
to www.freescale.com.  
The DSP56374 supports digital audio applications  
requiring sound field processing, acoustic equalization,  
and other digital audio algorithms. The DSP56374 uses  
the high performance, single-clock-per-cycle DSP56300  
core family of programmable CMOS digital signal  
processors (DSPs) combined with the audio signal  
processing capability of the Freescale Semiconductor,  
Inc. Symphony™ DSP family, as shown in Figure 1.  
Significant architectural enhancements include a barrel  
shifter, 24-bit addressing, and direct memory access  
© Freescale Semiconductor, Inc., 2004, 2005, 2006, 2007. All rights reserved.  

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