DSP56309
Rev. 7, 2/2005
Freescale Semiconductor
Technical Data Advance Information
DSP56309
24-Bit Digital Signal Processor
16
6
6
3
Memory Expansion Area
The DSP56309 is intended
for applications benefiting
from a large amount of
internal memory, such as
wireless infrastructure
applications.
Triple
Timer
X Data
RAM
Y Data
RAM
PrograM
RAM
HI08
ESSI
SCI
7168 × 24
7168 × 24
20480 × 24
bits
bits
bits
(default)
(default)
(default)
Peripheral
Expansion Area
YAB
18
Address
External
XAB
PAB
DAB
Generation
Unit
Address
Bus
Address
Switch
Six-Channel
DMA Unit
External
Bus
24-Bit
13
Interface
and Inst.
Cache
Bootstrap
ROM
DSP56300
Core
Control
Control
DDB
YDB
XDB
PDB
GDB
24
External
Data Bus
Switch
Internal
Data
Bus
What’s New?
Rev. 7 includes the following
changes:
Data
Switch
•
Adds lead-free packaging and
part numbers.
Power
EXTAL
XTAL
Management
Clock
Generator
Data ALU
5
Program
Interrupt
Controller
Program
Decode
Program
Address
Generator
+
→
24 × 24 56 56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
JTAG
PLL
2
Controller
OnCE™
DE
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
RESET
PINIT/NMI
Figure 1. DSP56309 Block Diagram
The DSP56309 is a member of the DSP56300 core family of programmable CMOS DSPs. The DSP56300 core
includes a barrel shifter, 24-bit addressing, an instruction cache, and direct memory access (DMA). The DSP56309
offers 100 MMACS at 3.0–3.6 V using an internal 100 MHz clock. The large internal memory is ideal for wireless
infrastructure and wireless local-loop applications. The DSP56300 core family offers a new level of performance in
speed and power provided by its rich instruction set and low-power dissipation, thus enabling a new generation of
wireless, multimedia, and telecommunications products.
Note: This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 1996, 2005. All rights reserved.