DSP56311
Rev. 8, 2/2005
Freescale Semiconductor
Technical Data
DSP56311
24-Bit Digital Signal Processor
3
16
6
6
Memory Expansion Area
The DSP56311 is intended
for applications requiring a
large amount of internal
memory, such as networking
and wireless infrastructure
applications. The onboard
EFCOP can accelerate
Program
RAM
Triple
Timer
32 K × 24 bits
SCI
HI08
ESSI
EFCOP
or
X Data
RAM
Y Data
RAM
31 K × 24 bits
and
48 K × 24 bits 48 K × 24 bits
Instruction
Cache
1024 × 24 bits
Peripheral
Expansion Area
general filtering applications,
such as echo-cancellation
applications, correlation, and
general-purpose convolution-
based algorithms.
YAB
Address
Generation
Unit
External
Address
Bus
XAB
PAB
DAB
18
Address
Switch
Six Channel
DMA Unit
External
Bus
24-Bit
DSP56300
Core
13
Interface
and
Bootstrap
ROM
Control
I - Cache
Control
DDB
YDB
XDB
PDB
GDB
External
Data
Bus
Internal
Data
Bus
24
What’s New?
Rev. 8 includes the following
changes:
Switch
Data
Switch
•
Adds lead-free packaging and
part numbers.
Power
Management
Data ALU
5
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Clock
Generator
+
→
24 × 24 56 56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
JTAG
PLL
OnCE™
DE
EXTAL
XTAL
RESET
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
PCAP
PINIT/NMI
Figure 1. DSP56311 Block Diagram
The Freescale DSP56311, a member of the DSP56300 DSP family, supports network applications with general filtering
operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations enhancing
signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance.
Like the other DSP56300 family members, the DSP56311 uses a high-performance, single-clock-cycle-per- instruction engine
(DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA)
controller (see Figure 1). The DSP56311 performs at up to 150 million multiply-accumulates per second (MMACS), attaining
up to 300 MMACS when the EFCOP is in use. It operates with an internal 150 MHz clock with a 1.8 volt core and
independent 3.3 volt input/output (I/O) power.
© Freescale Semiconductor, Inc., 1999, 2005. All rights reserved.