Technical Data
Advance Information
DSP56309/D
Rev. 2, 1/2002
24-Bit Digital Signal
Processor
16
6
6
3
Memory Expansion Area
Triple
Timer
X Data
RAM
7168 × 24
bits
Y Data
RAM
7168 × 24
bits
PrograM
RAM
20480 × 24
bits
HI08
ESSI
SCI
(default)
(default)
(default)
Peripheral
Expansion Area
The DSP56309 is
intended for
applications benefiting
from a large amount of
on-chip memory, such
as wireless
YAB
18
Address
External
XAB
PAB
DAB
Generation
Unit
Address
Bus
Address
Switch
Six-Channel
DMA Unit
External
Bus
24-Bit
13
Interface
and Inst.
Cache
Bootstrap
ROM
DSP56300
Core
Control
Control
infrastructure
applications.
DDB
YDB
XDB
PDB
GDB
24
External
Data Bus
Switch
Internal
Data
Bus
Data
Switch
Power
Management
EXTAL
XTAL
Clock
Generator
Data ALU
5
Program
Interrupt
Controller
Program
Decode
Program
Address
Generator
+
→
56-bit MAC
24 × 24 56
JTAG
Two 56-bit Accumulators
56-bit Barrel Shifter
PLL
2
Controller
OnCE™
DE
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
RESET
PINIT/NMI
Figure 1. DSP56309 Block Diagram
The DSP56309 is a member of the DSP56300 DSP56309 offers 100 MIPS at 3.0–3.6 V
core family of programmable CMOS digital
signal processors (DSPs). This family uses a
high performance, single-clock-cycle-per-
instruction engine providing a two-fold
using an internal 100 MHz clock. The large
on-chip memory is ideal for wireless
infrastructure and wireless local-loop
applications. The DSP56300 core family
performance increase over Motorola’s popular offers a new level of performance in speed
DSP56000 core, while retaining code and power provided by its rich instruction set
compatibility. The DSP56300 core includes a and low-power dissipation, thus enabling a
barrel shifter, 24-bit addressing, an instruction new generation of wireless, multimedia, and
cache, and direct memory access (DMA). The telecommunications products.
Note: This document contains information on a new product. Specifications and information herein are subject to change without notice.