Datasheet > DSP56311

DSP56311

更新时间： 2024-02-27 23:34:09

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		数字信号处理器
页数	文件大小	规格书
96页	1669K
描述
24-Bit Digital Signal Processor

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数据手册

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DSP56311 数据手册

DSP56311

Rev. 8, 2/2005

Freescale Semiconductor

Technical Data

DSP56311

24-Bit Digital Signal Processor

Memory Expansion Area

The DSP56311 is intended

for applications requiring a

large amount of internal

memory, such as networking

and wireless infrastructure

applications. The onboard

EFCOP can accelerate

Program

RAM

Triple

Timer

32 K × 24 bits

SCI

HI08

ESSI

EFCOP

X Data

RAM

Y Data

RAM

31 K × 24 bits

and

48 K × 24 bits 48 K × 24 bits

Instruction

Cache

1024 × 24 bits

Peripheral

Expansion Area

general filtering applications,

such as echo-cancellation

applications, correlation, and

general-purpose convolution-

based algorithms.

YAB

Address

Generation

Unit

External

Address

Bus

XAB

PAB

DAB

Address

Switch

Six Channel

DMA Unit

External

Bus

24-Bit

DSP56300

Core

Interface

and

Bootstrap

ROM

Control

I - Cache

Control

DDB

YDB

XDB

PDB

GDB

External

Data

Bus

Internal

Data

Bus

What’s New?

Rev. 8 includes the following

changes:

Switch

Data

Switch

•

Adds lead-free packaging and

part numbers.

Power

Management

Data ALU

Program

Interrupt

Controller

Program

Decode

Controller

Program

Address

Generator

Clock

Generator

→

24 × 24 56 56-bit MAC

Two 56-bit Accumulators

56-bit Barrel Shifter

JTAG

PLL

OnCE™

EXTAL

XTAL

RESET

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

PCAP

PINIT/NMI

Figure 1. DSP56311 Block Diagram

The Freescale DSP56311, a member of the DSP56300 DSP family, supports network applications with general filtering

operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations enhancing

signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance.

Like the other DSP56300 family members, the DSP56311 uses a high-performance, single-clock-cycle-per- instruction engine

(DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA)

controller (see Figure 1). The DSP56311 performs at up to 150 million multiply-accumulates per second (MMACS), attaining

up to 300 MMACS when the EFCOP is in use. It operates with an internal 150 MHz clock with a 1.8 volt core and

independent 3.3 volt input/output (I/O) power.

12 3 4 5 6 7...96

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与DSP56311相关器件

型号	品牌	获取价格	描述	数据表
DSP56311CE1K34A	MOTOROLA	获取价格	DSP56311 Device Errata for Mask
DSP56311EVMIG_D	ETC	获取价格	DSP56311EVMIG DSP56311EVM Sample Code
DSP56311EVMUM	ETC	获取价格	DSP56311 Evaluation Module Hardware Reference Manual
DSP56311FACT	ETC	获取价格	DSP56311 Higher performance programmable DSP for demanding voice and data applications
DSP56311UM	ETC	获取价格	DSP56311 24-Bit Digital Signal Processor Users Manual
DSP56311UMAD	ETC	获取价格	DSP56311 Users Manual Addendum
DSP56311VF150	FREESCALE	获取价格	24-Bit Digital Signal Processor
DSP56311VF150	MOTOROLA	获取价格	24-BIT, 150 MHz, OTHER DSP, PBGA196, MOLD ARRAY PROCESS, BGA-196
DSP56311VF150B1	NXP	获取价格	IC,DSP,24-BIT,CMOS,BGA,196PIN,PLASTIC
DSP56311VF150R2	MOTOROLA	获取价格	Digital Signal Processor, 24-Ext Bit, 150MHz, CMOS, PBGA196, MAP ARRAY PROCESS, BGA-196

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