June 1989
54LS164/DM54LS164/DM74LS164
8-Bit Serial In/Parallel Out Shift Registers
General Description
Features
Y
Gated (enable/disable) serial inputs
These 8-bit shift registers feature gated serial inputs and an
asynchronous clear. A low logic level at either input inhibits
entry of the new data, and resets the first flip-flop to the low
level at the next clock pulse, thus providing complete con-
trol over incoming data. A high logic level on either input
enables the other input, which will then determine the state
of the first flip-flop. Data at the serial inputs may be changed
while the clock is high or low, but only information meeting
the setup and hold time requirements will be entered. Clock-
ing occurs on the low-to-high level transition of the clock
input. All inputs are diode-clamped to minimize transmis-
sion-line effects.
Y
Fully buffered clock and serial inputs
Y
Asynchronous clear
Y
Typical clock frequency 36 MHz
Y
Typical power dissipation 80 mW
Y
Alternate Military/Aerospace device (54LS164) is avail-
able. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Function Table
Dual-In-Line Package
Inputs
Clock
Outputs
Clear
A
B
Q
A
Q
...
Q
H
B
L
H
H
H
H
X
L
X
X
H
L
X
X
H
X
L
L
L
...
...
...
...
...
L
Q
Q
B0
Q
An
Q
An
Q
An
Q
H0
Q
Gn
Q
Gn
Q
Gn
A0
H
u
u
u
L
L
X
e
e
e
H
X
High Level (steady state), L
Low Level (steady state)
Don’t Care (any input, including transitions)
e
Transition from low to high level
u
Q
e
indicated steady-state input conditions were established.
,
Q
B0
,
Q
H0
The level of
Q , Q , or Q , respectively, before the
A B H
A0
e
the clock; indicates a one-bit shift.
Q
, Q
The level of Q or Q before the most recent
A
transition of
u
An
Gn
G
TL/F/6398–1
Order Number 54LS164DMQB, 54LS164FMQB,
54LS164LMQB, DM54LS164J, DM54LS164W,
DM74LS164M or DM74LS164N
See NS Package Number E20A,
J14A, M14A, N14A or W14B
Logic Diagram
TL/F/6398–2
C
1995 National Semiconductor Corporation
TL/F/6398
RRD-B30M105/Printed in U. S. A.