May 1992
DM54LS165/DM74LS165 8-Bit Parallel
In/Serial Output Shift Registers
General Description
This device is an 8-bit serial shift register which shifts data in
Data at the parallel inputs are loaded directly into the regis-
ter on a high-to-low transition of the shift/load input, regard-
less of the logic levels on the clock, clock inhibit, or serial
inputs.
the direction of Q toward Q when clocked. Parallel-in ac-
H
A
cess is made available by eight individual direct data inputs,
which are enabled by a low level at the shift/load input.
These registers also feature gated clock inputs and comple-
mentary outputs from the eighth bit.
Features
Y
Clocking is accomplished through a 2-input NOR gate, per-
mitting one input to be used as a clock-inhibit function. Hold-
ing either of the clock inputs high inhibits clocking, and hold-
ing either clock input low with the load input high enables
the other clock input. The clock-inhibit input should be
changed to the high level only while the clock input is high.
Parallel loading is inhibited as long as the load input is high.
Complementary outputs
Y
Direct overriding (data) inputs
Y
Gated clock inputs
Y
Parallel-to-serial data conversion
Y
Typical frequency 35 MHz
Y
Typical power dissipation 105 mW
Connection Diagram
Dual-In-Line Package
TL/F/6399–1
Order Number DM54LS165J, DM54LS165W, DM74LS165WM or DM74LS165N
See NS Package Number J16A, M16B, N16E or W16A
Function Table
Inputs
Clock
Internal
Outputs
Output
Shift/
Load
Clock
Parallel
A...H
Serial
Q
H
Inhibit
Q
A
Q
B
L
H
H
H
H
X
L
X
X
X
H
L
a...h
X
a
b
h
L
Q
A0
Q
Q
Q
Q
Q
H0
Q
Gn
Q
Gn
Q
H0
B0
An
An
B0
L
X
H
u
L
X
L
u
H
X
X
X
Q
A0
e
e
e
Low Level (steady state)
H
X
High Level (steady state), L
Don’t Care (any input, including transitions)
e
Transition from low-to-high level
u
a...h
e
The level of steady-state input at inputs A through H, respectively.
e
The level of Q , Q , or Q , respectively, before the indicated steady-state input conditions were established.
A B H
Q
Q
, Q , Q
B0
A0
H0
e
, Q
The level of Q or Q , respectively, before the most recent
A
transition of the clock.
u
An
Gn
G
C
1995 National Semiconductor Corporation
TL/F/6399
RRD-B30M105/Printed in U. S. A.