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DM74LS169AN PDF预览

DM74LS169AN

更新时间: 2024-09-13 23:00:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 217K
描述
Synchronous 4-Bit Up/Down Binary Counter

DM74LS169AN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.23
计数方向:BIDIRECTIONAL系列:LS
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
长度:19.305 mm负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.008 A工作模式:SYNCHRONOUS
位数:4功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):34 mA传播延迟(tpd):32 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Counters最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:20 MHzBase Number Matches:1

DM74LS169AN 数据手册

 浏览型号DM74LS169AN的Datasheet PDF文件第2页浏览型号DM74LS169AN的Datasheet PDF文件第3页浏览型号DM74LS169AN的Datasheet PDF文件第4页浏览型号DM74LS169AN的Datasheet PDF文件第5页浏览型号DM74LS169AN的Datasheet PDF文件第6页浏览型号DM74LS169AN的Datasheet PDF文件第7页 
April 1998  
DM74LS169A  
Synchronous 4-Bit Up/Down Binary Counter  
the carry outputs. The carry output thus enabled will produce  
a low-level output pulse with a duration approximately equal  
to the high portion of the QA output when counting up, and  
approximately equal to the low portion of the QA output when  
counting down. This low-level overflow carry pulse can be  
used to enable successively cascaded stages. Transitions at  
the enable P or T inputs are allowed regardless of the level  
of the clock input. All inputs are diode clamped to minimize  
transmission-line effects, thereby simplifying system design.  
General Description  
This synchronous presettable counter features an internal  
carry look-ahead for cascading in high-speed counting appli-  
cations. Synchronous operation is provided by having all  
flip-flops clocked simultaneously, so that the outputs all  
change at the same time when so instructed by the  
count-enable inputs and internal gating. This mode of opera-  
tion helps eliminate the output counting spikes that are nor-  
mally associated with asynchronous (ripple clock) counters.  
A buffered clock input triggers the four master-slave flip-flops  
on the rising edge of the clock waveform.  
This counter features  
a fully independent clock circuit.  
Changes at control inputs (enable P, enable T, load, up/  
down), which modify the operating mode, have no effect until  
clocking occurs. The function of the counter (whether en-  
abled, disabled, loading, or counting) will be dictated solely  
by the conditions meeting the stable setup and hold times.  
This counter is fully programmable; that is, the outputs may  
each be preset either high or low. The load input circuitry al-  
lows loading with the carry-enable output of cascaded  
counters. As loading is synchronous, setting up a low level at  
the load input disables the counter and causes the outputs to  
agree with the data inputs after the next clock pulse.  
Features  
n Fully synchronous operation for counting and  
programming.  
n Internal look-ahead for fast counting.  
n Carry output for n-bit cascading.  
n Fully independent clock circuit  
The carry look-ahead circuitry permits cascading counters  
for n-bit synchronous applications without additional gating.  
Both count-enable inputs (P and T) must be low to count.  
The direction of the count is determined by the level of the  
up/down input. When the input is high, the counter counts  
up; when low, it counts down. Input T is fed forward to enable  
Connection Diagram  
Dual-In-Line Package  
DS006401-1  
Order Number 54LS169DMQB, 54LS169FMQB, 54LS169LMQB,  
DM54LS169AJ, DM54LS169AW, DM74LS169AM or DM74LS169AN  
See Package Number E20A, J16A, M16A, N16E or W16A  
© 1998 Fairchild Semiconductor Corporation  
DS006401  
www.fairchildsemi.com  

DM74LS169AN 替代型号

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