Datasheet > DM74LS173AMX

DM74LS173AMX

更新时间： 2024-09-15 20:01:35

品牌	Logo	应用领域
德州仪器 - TI		光电二极管输出元件逻辑集成电路触发器
页数	文件大小	规格书
8页	157K
描述
LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.150 INCH, PLASTIC, SOIC-16

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DM74LS173AMX 技术参数

生命周期：	Obsolete	包装说明：	SOP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.83	其他特性：	WITH HOLD MODE; WITH DUAL OUTPUT ENABLE
系列：	LS	JESD-30 代码：	R-PDSO-G16
长度：	9.9 mm	负载电容（CL）：	50 pF
逻辑集成电路类型：	D FLIP-FLOP	位数：	4
功能数量：	1	端子数量：	16
最高工作温度：	70 °C	最低工作温度：
输出特性：	3-STATE	输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
最大电源电流（ICC）：	30 mA	传播延迟（tpd）：	28 ns
认证状态：	Not Qualified	座面最大高度：	1.75 mm
最大供电电压 (Vsup)：	5.25 V	最小供电电压 (Vsup)：	4.75 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	TTL	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	触发器类型：	POSITIVE EDGE
宽度：	3.9 mm	最小 fmax：	20 MHz
Base Number Matches：	1

DM74LS173AMX 数据手册

May 1992

54LS173/DM74LS173A

TRI-STATE 4-Bit D-Type Register

General Description

This four-bit register contains D-type flip-flops with totem-

pole TRI-STATE outputs, capable of driving highly capaci-

tive or low-impedance loads. The high-impedance state and

increased high-logic-level drive provide these flip-flops with

the capability of driving the bus lines in a bus-organized sys-

tem without need for interface or pull-up components.

To minimize the possibility that two outputs will attempt to

take a common bus to opposite logic levels, the output con-

trol circuitry is designed so that the average output disable

times are shorter than the average output enable times.

Features

Gated enable inputs are provided for controlling the entry of

data into the flip-flops. When both data-enable inputs are

low, data at the D inputs are loaded into their respective flip-

flops on the next positive transition of the buffered clock

input. Gate output control inputs are also provided. When

both are low, the normal logic states of the four outputs are

available for driving the loads or bus lines. The outputs are

disabled independently from the level of the clock by a high

logic level at either output control input. The outputs then

present a high impedance and neither load nor drive the bus

line. Detailed operation is given in the truth table.

TRI-STATE outputs interface directly with system bus

Gated output control lines for enabling or disabling the

outputs

Fully independent clock eliminates restrictions for oper-

ating in one of two modes:

Parallel load

Do nothing (hold)

For application as bus buffer registers

Connection Diagram

Function Table

Dual-In-Line Package

Inputs

Data

Output

Clear

Clock

Enable

Data

When either M or N (or both) is (are) high the output is

disabled to the high-impedance state; however,

sequential operation of the flip-flops is not affected.

High Level (Steady State)

Low Level (Steady State)

TL/F/6403–1

Order Number 54LS173DMQB, 54LS173FMQB,

54LS173LMQB, DM74LS173AM or DM74LS173AN

See NS Package Number E20A, J16A,

Low-to-High Level Transition

Don’t Care (Any Input Including Transitions)

Were Established.

The Level of Q Before the Indicated Steady State Input Conditions

M16A, N16E or W16A

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

1995 National Semiconductor Corporation

TL/F/6403

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6 7 8

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与DM74LS173AMX相关器件

型号	品牌	获取价格	描述	数据表
DM74LS173AN	NSC	获取价格	TRI-STATE 4-BIT D-TYPE REGISTER
DM74LS173AN/A+	ETC	获取价格	Quad D-Type Flip-Flop
DM74LS173AN/B+	ETC	获取价格	Quad D-Type Flip-Flop
DM74LS173J	TI	获取价格	IC,FLIP-FLOP,QUAD,D TYPE,LS-TTL,DIP,16PIN,CERAMIC
DM74LS173J/A+	ETC	获取价格	Quad D-Type Flip-Flop
DM74LS173M	ETC	获取价格	Quad D-Type Flip-Flop
DM74LS173N	TI	获取价格	IC,FLIP-FLOP,QUAD,D TYPE,LS-TTL,DIP,16PIN,PLASTIC
DM74LS173N/A+	ETC	获取价格	Quad D-Type Flip-Flop
DM74LS173N/B+	ETC	获取价格	Quad D-Type Flip-Flop
DM74LS173W	TI	获取价格	IC,FLIP-FLOP,QUAD,D TYPE,LS-TTL,FP,16PIN,CERAMIC

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