Datasheet > DM74LS169AMX

DM74LS169AMX

更新时间： 2024-09-13 23:47:39

品牌	Logo	应用领域
其他 - ETC		计数器触发器逻辑集成电路光电二极管
页数	文件大小	规格书
7页	75K
描述
Synchronous Up/Down Counter

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DM74LS169AMX 数据手册

August 1986

Revised April 2000

DM74LS169A

Synchronous 4-Bit Up/Down Binary Counter

enabled will produce a low-level output pulse with a dura-

tion approximately equal to the high portion of the Q_Aout-

General Description

This synchronous presettable counter features an internal

carry look-ahead for cascading in high-speed counting

applications. Synchronous operation is provided by having

all flip-flops clocked simultaneously, so that the outputs all

change at the same time when so instructed by the count-

enable inputs and internal gating. This mode of operation

helps eliminate the output counting spikes that are nor-

mally associated with asynchronous (ripple clock)

counters. A buffered clock input triggers the four master-

slave flip-flops on the rising edge of the clock waveform.

put when counting UP, and approximately equal to the low

portion of the Q_Aoutput when counting DOWN. This low-

level overflow carry pulse can be used to enable succes-

sively cascaded stages. Transitions at the enable P or T

inputs are allowed regardless of the level of the clock input.

All inputs are diode clamped to minimize transmission-line

effects, thereby simplifying system design.

This counter features a fully independent clock circuit.

Changes at control inputs (enable P, enable T, load, UP/

DOWN), which modify the operating mode, have no effect

until clocking occurs. The function of the counter (whether

enabled, disabled, loading, or counting) will be dictated

solely by the conditions meeting the stable setup and hold

times.

This counter is fully programmable; that is, the outputs may

each be preset either HIGH or LOW. The load input cir-

cuitry allows loading with the carry-enable output of cas-

caded counters. As loading is synchronous, setting up a

low level at the load input disables the counter and causes

the outputs to agree with the data inputs after the next

clock pulse.

Features

■ Fully synchronous operation for counting and

The carry look-ahead circuitry permits cascading counters

for n-bit synchronous applications without additional gating.

Both count-enable inputs (P and T) must be LOW to count.

The direction of the count is determined by the level of the

UP/DOWN input. When the input is HIGH, the counter

counts UP; when LOW, it counts DOWN. Input T is fed for-

ward to enable the carry outputs. The carry output thus

programming.

■ Internal look-ahead for fast counting.

■ Carry output for n-bit cascading.

■ Fully independent clock circuit

Ordering Code:

Order Number Package Number

Package Description

DM74LS169AM

DM74LS169AN

M16A

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

DS006401

www.fairchildsemi.com

12 3 4 5 6 7

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与DM74LS169AMX相关器件

型号	品牌	获取价格	描述	数据表
DM74LS169AN	FAIRCHILD	获取价格	Synchronous 4-Bit Up/Down Binary Counter
DM74LS169AN	NSC	获取价格	Synchronous 4-Bit Up/Down Binary Counter
DM74LS169AN/A+	NSC	获取价格	IC,COUNTER,UP/DOWN,4-BIT BINARY,LS-TTL,DIP,16PIN,PLASTIC
DM74LS169AN/B+	NSC	获取价格	IC,COUNTER,UP/DOWN,4-BIT BINARY,LS-TTL,DIP,16PIN,PLASTIC
DM74LS169J/A+	NSC	获取价格	IC,COUNTER,UP/DOWN,4-BIT BINARY,LS-TTL,DIP,16PIN,CERAMIC
DM74LS169N	NSC	获取价格	IC,COUNTER,UP/DOWN,4-BIT BINARY,LS-TTL,DIP,16PIN,PLASTIC
DM74LS169N/A+	ETC	获取价格	Synchronous Up/Down Counter
DM74LS169N/B+	NSC	获取价格	IC,COUNTER,UP/DOWN,4-BIT BINARY,LS-TTL,DIP,16PIN,PLASTIC
DM74LS170	NSC	获取价格	4x4 REGISTER FILE WITH OPEN-COLLECTOR OUTPUTS
DM74LS170J	NSC	获取价格	IC,REGISTER FILE,LS-TTL,DIP,16PIN,CERAMIC

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