DM74LS165

更新时间： 2024-09-09 23:00:43

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		移位寄存器
页数	文件大小	规格书
6页	76K
描述
8-Bit Parallel In/Serial Output Shift Registers

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数据手册

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DM74LS165 数据手册

August 1986

Revised March 2000

DM74LS165

8-Bit Parallel In/Serial Output Shift Registers

General Description

Features

■ Complementary outputs

■ Direct overriding (data) inputs

■ Gated clock inputs

This device is an 8-bit serial shift register which shifts data

in the direction of Q_Atoward Q_Hwhen clocked. Parallel-in

access is made available by eight individual direct data

inputs, which are enabled by a low level at the shift/load

input. These registers also feature gated clock inputs and

complementary outputs from the eighth bit.

■ Parallel-to-serial data conversion

■ Typical frequency 35 MHz

■ Typical power dissipation 105 mW

Clocking is accomplished through a 2-input NOR gate, per-

mitting one input to be used as a clock-inhibit function.

Holding either of the clock inputs HIGH inhibits clocking,

and holding either clock input LOW with the load input

HIGH enables the other clock input. The clock-inhibit input

should be changed to the high level only while the clock

input is HIGH. Parallel loading is inhibited as long as the

load input is HIGH. Data at the parallel inputs are loaded

directly into the register on a HIGH-to-LOW transition of the

shift/load input, regardless of the logic levels on the clock,

clock inhibit, or serial inputs.

Ordering Code:

Order Number Package Number

Package Description

DM74LS165M

DM74LS165WM

DM74LS165N

M16A

M16B

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Internal

Shift/ Clock Clock Serial Parallel Outputs Output

Q_AQ_B

Q_H

Load Inhibit

A...H

a...h

↑

Q_A0Q_B0Q_H0

Q_AnQ_Gn

↑

Q_A0Q_B0Q_H0

H = HIGH Level (steady state)

L = LOW Level (steady state)

X = Don't Care (any input, including transitions)

↑ = Transition from LOW-to-HIGH level

a...h = The level of steady-state input at inputs A through H, respectively.

, Q , Q = The level of Q , Q , or Q , respectively, before the

B0 H0 A B H

indicated steady-state input conditions were established.

, Q = The level of Q or Q , respectively, before the most recent

↑ transition of the clock.

DS006399

www.fairchildsemi.com

12 3 4 5 6

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与DM74LS165相关器件

型号	品牌	获取价格	描述	数据表
DM74LS165J/A+	TI	获取价格	IC,SHIFT REGISTER,LS-TTL,DIP,16PIN,CERAMIC
DM74LS165M	FAIRCHILD	获取价格	8-Bit Parallel In/Serial Output Shift Registers
DM74LS165N	FAIRCHILD	获取价格	8-Bit Parallel In/Serial Output Shift Registers
DM74LS165N	NSC	获取价格	8-Bit Parallel In/Serial Output Shift Registers
DM74LS165N/A+	NSC	获取价格	IC,SHIFT REGISTER,LS-TTL,DIP,16PIN,PLASTIC
DM74LS165N/A+	TI	获取价格	IC,SHIFT REGISTER,LS-TTL,DIP,16PIN,PLASTIC
DM74LS165N/B+	NSC	获取价格	IC,SHIFT REGISTER,LS-TTL,DIP,16PIN,PLASTIC
DM74LS165N/B+	TI	获取价格	IC,SHIFT REGISTER,LS-TTL,DIP,16PIN,PLASTIC
DM74LS165WM	FAIRCHILD	获取价格	8-Bit Parallel In/Serial Output Shift Registers
DM74LS165WM	NSC	获取价格	8-Bit Parallel In/Serial Output Shift Registers

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