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DM74LS165M PDF预览

DM74LS165M

更新时间: 2024-09-09 23:00:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 移位寄存器
页数 文件大小 规格书
6页 76K
描述
8-Bit Parallel In/Serial Output Shift Registers

DM74LS165M 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.3
计数方向:RIGHT系列:LS
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm逻辑集成电路类型:PARALLEL IN SERIAL OUT
最大频率@ Nom-Sup:20000000 Hz位数:8
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):47 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Shift Registers
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:20 MHz

DM74LS165M 数据手册

 浏览型号DM74LS165M的Datasheet PDF文件第2页浏览型号DM74LS165M的Datasheet PDF文件第3页浏览型号DM74LS165M的Datasheet PDF文件第4页浏览型号DM74LS165M的Datasheet PDF文件第5页浏览型号DM74LS165M的Datasheet PDF文件第6页 
August 1986  
Revised March 2000  
DM74LS165  
8-Bit Parallel In/Serial Output Shift Registers  
General Description  
Features  
Complementary outputs  
Direct overriding (data) inputs  
Gated clock inputs  
This device is an 8-bit serial shift register which shifts data  
in the direction of QA toward QH when clocked. Parallel-in  
access is made available by eight individual direct data  
inputs, which are enabled by a low level at the shift/load  
input. These registers also feature gated clock inputs and  
complementary outputs from the eighth bit.  
Parallel-to-serial data conversion  
Typical frequency 35 MHz  
Typical power dissipation 105 mW  
Clocking is accomplished through a 2-input NOR gate, per-  
mitting one input to be used as a clock-inhibit function.  
Holding either of the clock inputs HIGH inhibits clocking,  
and holding either clock input LOW with the load input  
HIGH enables the other clock input. The clock-inhibit input  
should be changed to the high level only while the clock  
input is HIGH. Parallel loading is inhibited as long as the  
load input is HIGH. Data at the parallel inputs are loaded  
directly into the register on a HIGH-to-LOW transition of the  
shift/load input, regardless of the logic levels on the clock,  
clock inhibit, or serial inputs.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS165M  
DM74LS165WM  
DM74LS165N  
M16A  
M16B  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Inputs  
Internal  
Shift/ Clock Clock Serial Parallel Outputs Output  
QA QB  
QH  
Load Inhibit  
A...H  
a...h  
X
L
H
H
H
H
X
L
X
L
X
X
H
L
a
b
h
QA0 QB0 QH0  
L
X
H
L
QAn QGn  
QAn QGn  
L
X
H
X
X
X
QA0 QB0 QH0  
H = HIGH Level (steady state)  
L = LOW Level (steady state)  
X = Don't Care (any input, including transitions)  
↑ = Transition from LOW-to-HIGH level  
a...h = The level of steady-state input at inputs A through H, respectively.  
Q
Q
, Q , Q = The level of Q , Q , or Q , respectively, before the  
B0 H0 A B H  
A0  
indicated steady-state input conditions were established.  
, Q = The level of Q or Q , respectively, before the most recent  
An  
Gn  
A
G
transition of the clock.  
© 2000 Fairchild Semiconductor Corporation  
DS006399  
www.fairchildsemi.com  

DM74LS165M 替代型号

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