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CY7C1462KV25-200AXC PDF预览

CY7C1462KV25-200AXC

更新时间： 2024-11-17 00:46:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
32页 830K
描述
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)

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中文翻译

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CY7C1462KV25-200AXC 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：LQFP,Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.79其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PQFP-G100长度：20 mm
内存密度：37748736 bit内存集成电路类型：ZBT SRAM
内存宽度：18功能数量：1
端子数量：100字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：2MX18封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
座面最大高度：1.6 mm最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

CY7C1462KV25-200AXC 数据手册

 浏览型号CY7C1462KV25-200AXC的Datasheet PDF文件第2页浏览型号CY7C1462KV25-200AXC的Datasheet PDF文件第3页浏览型号CY7C1462KV25-200AXC的Datasheet PDF文件第4页浏览型号CY7C1462KV25-200AXC的Datasheet PDF文件第5页浏览型号CY7C1462KV25-200AXC的Datasheet PDF文件第6页浏览型号CY7C1462KV25-200AXC的Datasheet PDF文件第7页 
CY7C1460KV25/CY7C1462KV25  
CY7C1460KVE25/CY7C1462KVE25  
36-Mbit (1M × 36/2M × 18)  
Pipelined SRAM  
with NoBL™ Architecture (With ECC)  
36-Mbit (1M  
× 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)  
Features  
Functional Description  
The CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/  
CY7C1462KVE25 are 2.5 V, 1M × 36/2M × 18 synchronous  
pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic,  
respectively. They are designed to support unlimited true  
back-to-back read/write operations with no wait states. The  
CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/  
CY7C1462KVE25 are equipped with the advanced NoBL logic  
required to enable consecutive read/write operations with data  
being transferred on every clock cycle. This feature dramatically  
improves the throughput of data in systems that require frequent  
write/read transitions. The CY7C1460KV25/CY7C1462KV25/  
CY7C1460KVE25/CY7C1462KVE25 are pin-compatible and  
functionally equivalent to ZBT devices.  
■ Pin-compatible and functionally equivalent to ZBT™  
■ Supports 250 MHz bus operations with zero wait states  
❐ Availablespeedgradesare250MHz, 200MHz, and167MHz  
■ Internally self-timed output buffer control to eliminate the need  
to use asynchronous OE  
■ Fully registered (inputs and outputs) for pipelined operation  
■ Byte Write capability  
■ 2.5 V core power supply  
■ 2.5 V I/O power supply  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. All data outputs pass through output  
registers controlled by the rising edge of the clock. The clock  
input is qualified by the clock enable (CEN) signal, which when  
deasserted suspends operation and extends the previous clock  
cycle. Write operations are controlled by the byte write selects  
■ Fast clock-to-output times  
❐ 2.5 ns (for 250 MHz device)  
■ Clock enable (CEN) pin to suspend operation  
■ Synchronous self-timed writes  
BWa–BWd  
for  
CY7C1460KV25/CY7C1460KVE25  
and  
■ CY7C1460KV25, CY7C1462KV25, CY7C1460KVE25 and  
CY7C1462KVE25 available in JEDEC-standard Pb-free  
100-pin TQFP, and Pb-free and non Pb-free 165-ball FBGA  
packages.  
BWa–BWb for CY7C1462KV25/CY7C1462KVE25 and a write  
enable (WE) input. All writes are conducted with on-chip  
synchronous self-timed write circuitry.  
Three synchronous chip enables (CE1, CE2, CE3) and an  
asynchronous output enable (OE) provide for easy bank  
selection and output three-state control. In order to avoid bus  
contention, the output drivers are synchronously three-stated  
during the data portion of a write sequence.  
■ IEEE 1149.1 JTAG-Compatible Boundary Scan  
■ Burst capability — linear or interleaved burst order  
■ “ZZ” sleep mode option  
■ On-chip error correction code (ECC) to reduce soft error rate  
(SER)  
Selection Guide  
Description  
Maximum access time  
250 MHz  
2.5  
200 MHz  
3.2  
167 MHz Unit  
3.4  
170  
190  
ns  
Maximum operating current  
× 18  
× 36  
220  
190  
mA  
240  
210  
Cypress Semiconductor Corporation  
Document Number: 001-66679 Rev. *J  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised February 7, 2018  
1234567...32

中文翻译

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与CY7C1462KV25-200AXC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1462KV25-250BZXC CYPRESS

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 		36-Mbit (1M × 36/2M × 18) Pipelined SRAM wi
CY7C1462KVE25 CYPRESS

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 		36-Mbit (1M × 36/2M × 18) Pipelined SRAM wi
CY7C1462KVE25-167BZI CYPRESS

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 		36-Mbit (1M × 36/2M × 18) Pipelined SRAM wi
CY7C1462KVE25-167BZI INFINEON

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 		Synchronous SRAM with ECC
CY7C1462KVE33 CYPRESS

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 		36-Mbit (1M × 36/2M × 18) Pipelined SRAM wi
CY7C1462KVE33-167AXC CYPRESS

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 		36-Mbit (1M × 36/2M × 18) Pipelined SRAM wi
CY7C1462KVE33-167AXC INFINEON

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 		Synchronous SRAM with ECC
CY7C1462V25 ETC

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 		Memory
CY7C1462V25-167AC CYPRESS

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 		ZBT SRAM, 2MX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1462V25-167BGC CYPRESS

获取价格

 		ZBT SRAM, 2MX18, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

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