CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
36-Mbit (1M × 36/2M × 18) Pipelined SRAM
with NoBL™ Architecture (With ECC)
36-Mbit (1M
× 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
Features
Functional Description
■ Pin-compatible and functionally equivalent to Zero Bus
Turnaround (ZBT™)
The CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 are
3.3 V, 1M × 36, and 2M × 18 synchronous pipelined burst SRAMs
with No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back read/write
■ Supports 250-MHz bus operations with zero wait states
❐ Available speed grades are 250, 200, and 167 MHz
operations
with
no
wait
states.
The
■ Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 devices
are equipped with the advanced (NoBL) logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle.
■ Fully-registered (inputs and outputs) for pipelined operation
■ Byte write capability
This feature dramatically improves the throughput of data in
systems that require frequent write and read transitions. The
CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 devices
are pin-compatible and functionally equivalent to ZBT devices.
■ 3.3-V power supply
■ 3.3-V/2.5-V I/O power supply
■ Fast clock-to-output time
❐ 2.5 ns (for 250-MHz device)
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ CY7C1460KV33,
CY7C1460KVE33,
CY7C1462KVE33
available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non Pb-free 165-ball FBGA packages
Write operations are controlled by the byte write selects
(BWa–BWd
for
CY7C1460KV33/CY7C1460KVE33
and
■ IEEE 1149.1 JTAG-compatible boundary scan
■ Burst capability—linear or interleaved burst order
■ “ZZ” sleep mode option
BWa–BWb for CY7C1462KVE33) and a write enable (WE) input.
All writes are conducted with on-chip synchronous self-timed
write circuitry.
Three synchronous chip enables (CE1, CE2, and CE3) and an
asynchronous output enable (OE) enable easy bank selection
and output tristate control. To avoid bus contention, the output
drivers are synchronously tristated during the data portion of a
write sequence.
■ On-chip Error Correction Code (ECC) to reduce Soft Error Rate
(SER)
Selection Guide
Description
Maximum access time
250 MHz
2.5
200 MHz
3.2
167 MHz Unit
3.4
170
190
ns
Maximum operating current
× 18
× 36
220
190
mA
240
210
Cypress Semiconductor Corporation
Document Number: 001-66680 Rev. *L
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 8, 2018