CY7C1460V33
CY7C1462V33
CY7C1464V33
PRELIMINARY
1M x 36/2M x 18/512K x 72 Pipelined SRAM
with NoBL™ Architecture
Clock Enable (CEN), Byte Write Selects (BWSa, BWSb, BWSc
,BWSd, BWSe, BWSf, BWSg ,BWSh), and read-write control
(WE). BWSc and BWSd apply to CY7C1460V33 and
CY7C1464V33 only. BWSe, BWSf, BWSg, and BWSh apply to
CY7C1464V33 only.
Features
• Zero Bus Latency , no dead cycles between write and
read cycles
• Fast clock speed: 250, 200, and 167 MHz
• Fast access time: 2.7, 3.0 and 3.5 ns
• Internally synchronized registered outputs eliminate
the need to control OE
• Single 3.3V –5% and +5% power supply VDD
• Separate VDDQ for 3.3V or 2.5V
• Single WE (Read/Write) control pin
• Positive clock-edge triggered, address, data, and
control signal registers for fully pipelined applications
• Interleaved or linear four-word burst capability
• Individual byte write (BWSa – BWSh) control (may be
tied LOW)
• CEN pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• JTAG boundary scan for BGA packaging version
• Available in 119-ball bump BGA, 165-ball FBGA
package and 100-pin TQFP packages (CY7C1460 and
CY7C1462). 209 FBGA package for CY7C1464.
Address and control signals are applied to the SRAM during
one clock cycle, and two cycles later, its associated data
occurs, either read or write.
A
Clock Enable (CEN) pin allows operation of the
CY7C1460V33, CY7C1462V33, and CY7C1464V33 to be
suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers
will hold their previous values.
There are three Chip Enable (CE1, CE2, CE3) pins that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is low, no new
memory operation can be initiated and any burst cycle in
progress is stopped. However, any pending data transfers
(read or write) will be completed. The data bus will be in high
impedance state two cycles after chip is deselected or a write
cycle is initiated.
The CY7C1460V33, CY7C1462V33, and CY7C1464V33
have an on-chip two-bit burst counter. In the burst mode,
CY7C1460V33, CY7C1462V33, and CY7C1464V33 provide
four cycles of data for a single address presented to the
SRAM. The order of the burst sequence is defined by the
MODE input pin. The MODE pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load
a new external address (ADV/LD = LOW) or increment the
internal burst counter (ADV/LD = HIGH).
Functional Description
The CY7C1460V33, CY7C1462V33, and CY7C1464V33
SRAMs are designed to eliminate dead cycles when transi-
tions from READ to WRITE or vice versa. These SRAMs are
optimized for 100 percent bus utilization and achieves Zero
Bus Latency. They integrate 1,048,576 x 36/2,097,152 x 18/
524,288 x 72 SRAM cells, respectively, with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. The Synchronous Burst SRAM family
employs high-speed, low-power CMOS designs using
advanced single-layer polysilicon, three-layer metal
technology. Each memory cell consists of six transistors.
Output Enable (OE) and burst sequence select (MODE) are
the asynchronous signals. OE can be used to disable the
outputs at any given time. ZZ may be tied to LOW if it is not
used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE1, CE2, and CE3), cycle start input (ADV/LD),
D
CLK
Data-In REG.
Logic Block Diagram
CE
Q
ADV/LD
A
x
CEN
CE
CONTROL
and WRITE
LOGIC
1Mx36
1
2Mx18
CE
CE
DQ
A
BWS
X
DP
X
2
X
X
512Kx72
DQ
DP
x
3
WE
X = a, b
, c, d
X = a, b, X= a, b,
c, d
MEMORY
ARRAY
X = 19:0
X = 20:0
x
1Mx36
c, d
BWS
x
X = a, b
X = a, b X = a, b
Mode
2Mx18
X = a, b
X = a, b,
X = a, b,
X = 18:0
512Kx72
c,d,e,f,g,h
c,d,e,f,g,h
c,d,e,f,g,h
OE
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05190 Rev. *C
Revised November 14, 2002
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