Datasheet > CY7C1462V25-167BZC

CY7C1462V25-167BZC

更新时间： 2024-09-29 03:22:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
26页	475K
描述
ZBT SRAM, 2MX18, 3.5ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165

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CY7C1462V25-167BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	15 X 17 MM, 1.20 MM HEIGHT, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92

CY7C1462V25-167BZC 数据手册

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CY7C1460V25

CY7C1462V25

CY7C1464V25

PRELIMINARY

1M x 36/2M x 18/512K x 72 Pipelined SRAM

with NoBL™ Architecture

Clock Enable (CEN), Byte Write Selects (BWS_a, BWS_b,

BWS_c,BWS_d,BWS_e, BWS_f, BWS_g, BWS_h), and read-write

control (WE). BWS_cand BWS_dapply to CY7C1460V25 and

CY7C1464V25 only.BWS_e, BWS_f,BWS_g, and BWS_happly to

CY7C1464V25 only

Features

• Zero Bus Latency , no dead cycles between write and

read cycles

• Fast clock speed: 250, 200, and 167 MHz

• Fast access time: 2.7, 3.0 and 3.5 ns

• Internally synchronized registered outputs eliminate

the need to control OE

• Single 2.5V ±5% power supply V_DD

• Separate V_DDQfor 2.5V or 1.8V I/O

• Single WE (Read/Write) control pin

Address and control signals are applied to the SRAM during

one clock cycle, and two cycles later, its associated data

occurs, either read or write.

Clock Enable (CEN) pin allows operation of the

CY7C1460V25,CY7C1462V25 and CY7C1464V25 to be

suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers

will hold their previous values.

• Positive clock-edge triggered, address, data, and

control signal registers for fully pipelined applications

• Interleaved or linear four-word burst capability

There are three Chip Enable (CE₁, CE₂, CE₃) pins that allow

the user to deselect the device when desired. If any one of

these three are not active when ADV/LD is low, no new

memory operation can be initiated and any burst cycle in

progress is stopped. However, any pending data transfers

(read or write) will be completed. The data bus will be in high

impedance state two cycles after chip is deselected or a write

cycle is initiated.

• Individualbytewrite(BWS_a–BWS_h)control(maybetied

LOW)

• CEN pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• JTAG boundary scan for BGA packaging version

• Available in 119-ball bump BGA, 165-ball FBGA

package and 100-pin TQFP packages (CY7C1460V25

and CY7C1462V25). 209 FBGA package for

CY7C1464V25

The CY7C1460V25,CY7C1462V25 and CY7C1464V25 have

an on-chip two-bit burst counter. In the burst mode,

CY7C1460V25,CY7C1462V25 and CY7C1464V25 provide

four cycles of data for a single address presented to the

SRAM. The order of the burst sequence is defined by the

MODE input pin. The MODE pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load

a new external address (ADV/LD = LOW) or increment the

internal burst counter (ADV/LD = HIGH)

Functional Description

The CY7C1460V25,CY7C1462V25 and CY7C1464V25

SRAMs are designed to eliminate dead cycles when transi-

tions from READ to WRITE or vice versa. These SRAMs are

optimized for 100 percent bus utilization and achieves Zero

Bus Latency. They integrate 1,048,576 x 36/2,097,152 x 18/

524,288 x 72 SRAM cells, respectively, with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. The Synchronous Burst SRAM family

employs high-speed, low-power CMOS designs using

advanced single layer polysilicon, three-layer metal

technology. Each memory cell consists of six transistors.

Output Enable (OE) and burst sequence select (MODE) are

the asynchronous signals. OE can be used to disable the

outputs at any given time. ZZ may be tied to LOW if it is not

used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE₁, CE₂, and CE₃), cycle start input (ADV/LD),

CLK

Data-In REG.

Logic Block Diagram

ADV/LD

CEN

CONTROL

and WRITE

LOGIC

1Mx36

2Mx18

512Kx72

BWS

MEMORY

ARRAY

BWS

X = a, b

, c, d

X= a, b,

c, d

X = a, b,

c, d

X = 19:0

X = 20:0

1Mx36

Mode

X = a, b

X = a, b X = a, b

2Mx18

X = a, b

X = a, b,

c,d,e,f,g,h

X = 18:0

512Kx72

c,d,e,f,g,h

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05191 Rev. *B

Revised November 14, 2002

12 3 4 5 6 7...26

中文翻译

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与CY7C1462V25-167BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1462V25-200BZC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 3ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1462V25-250AC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 2.7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1462V25-250BGC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 2.7ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1462V25-250BZC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 2.7ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1462V25-300AC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 2.3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1462V25-300BGC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 2.3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1462V25-300BZC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 2.3ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1462V33	ETC	获取价格	Memory
CY7C1462V33-167AC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1462V33-167BZC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 3.5ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165

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