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CY7C146-30JC PDF预览

CY7C146-30JC

更新时间： 2024-11-15 22:37:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
18页 341K
描述
2Kx8 Dual-Port Static RAM

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中文翻译

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CY7C146-30JC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：LCC包装说明：PLASTIC, LCC-52
针数：52Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.81Is Samacsys：N
最长访问时间：30 ns其他特性：AUTOMATIC POWER-DOWN; INTERRUPT FLAG
I/O 类型：COMMONJESD-30 代码：S-PQCC-J52
JESD-609代码：e0长度：19.1262 mm
内存密度：16384 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：8湿度敏感等级：1
功能数量：1端口数量：2
端子数量：52字数：2048 words
字数代码：2000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：2KX8输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC52,.8SQ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL峰值回流温度（摄氏度）：225
电源：5 V认证状态：Not Qualified
座面最大高度：5.08 mm最大待机电流：0.015 A
最小待机电流：4.5 V子类别：SRAMs
最大压摆率：0.17 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：19.1262 mmBase Number Matches：1

CY7C146-30JC 数据手册

 浏览型号CY7C146-30JC的Datasheet PDF文件第2页浏览型号CY7C146-30JC的Datasheet PDF文件第3页浏览型号CY7C146-30JC的Datasheet PDF文件第4页浏览型号CY7C146-30JC的Datasheet PDF文件第5页浏览型号CY7C146-30JC的Datasheet PDF文件第6页浏览型号CY7C146-30JC的Datasheet PDF文件第7页 
1CY7C132/CY7C136  
fax id: 5201  
CY7C132/CY7C136  
CY7C142/CY7C146  
2Kx8 Dual-Port Static RAM  
Features  
Functional Description  
• True Dual-Ported memory cells which allow simulta-  
neous reads of the same memory location  
• 2K x 8 organization  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 15 ns  
The CY7C132/CY7C136/CY7C142 and CY7C146 are  
high-speed CMOS 2K by 8 dual-port static RAMs. Two ports  
are provided to permit independent access to any location in  
memory. The CY7C132/ CY7C136 can be utilized as either a  
standalone 8-bit dual-port static RAM or as a MASTER du-  
al-port RAM in conjunction with the CY7C142/CY7C146  
SLAVE dual-port device in systems requiring 16-bit or greater  
word widths. It is the solution to applications requiring shared  
or buffered data such as cache memory for DSP, bit-slice, or  
multiprocessor designs.  
• Low operating power: I = 90 mA (max.)  
CC  
• Fully asynchronous operation  
• Automatic power-down  
• Master CY7C132/CY7C136 easily expands data bus  
width to 16 or more bits using slave CY7C142/CY7C146  
• BUSY output flag on CY7C132/CY7C136; BUSY input  
on CY7C142/CY7C146  
• INT flag for port-to-port communication (52-pin  
PLCC/PQFP versions)  
• Availablein 48-pin DIP (CY7C132/142), 52-pin PLCCand  
52-pin TQFP (CY7C136/146)  
• Pin-compatible and functionally equivalent to  
IDT7132/IDT7142  
Each port has independent control pins; chip enable (CE),  
write enable (R/W), and output enable (OE). BUSY flags are  
provided on each port. In addition, an interrupt flag (INT) is  
provided on each port of the 52-pin PLCC version. BUSY sig-  
nals that the port is trying to access the same location currently  
being accessed by the other port. On the PLCC version, INT  
is an interrupt flag indicating that data has been placed in a  
unique location (7FF for the left port and 7FE for the right port).  
An automatic power-down feature is controlled independently  
on each port by the chip enable (CE) pins.  
The CY7C132/CY7C142 are available in 48-pin DIP. The  
CY7C136/CY7C146 are available in 52-pin PLCC and PQFP.  
Logic Block Diagram  
Pin Configuration  
R/W  
L
R/W  
R
DIP  
Top View  
CE  
L
CE  
R
OE  
L
OE  
R
V
CC  
48  
1
CE  
L
R/W  
BUSY  
47  
CE  
R
R/W  
R
BUSY  
L
2
46  
3
L
45  
A
10L  
R
4
A
44  
5
I/O  
I/O  
OE  
10R  
I/O  
I/O  
7L  
L
7R  
0R  
I/O  
CONTROL  
I/O  
CONTROL  
A
0L  
OE  
43  
R
6
42  
7
A
0R  
A
A
A
0L  
[1]  
1L  
A
A
41  
2L  
1R  
8
[1]  
BUSY  
BUSY  
R
L
40  
9
2R  
3L  
A
A
A
39  
10  
3R  
4L  
A
A
A
10L  
10R  
0R  
MEMORY  
ARRAY  
A
A
ADDRESS  
DECODER  
5L  
38  
37  
ADDRESS  
DECODER  
11  
12  
4R  
A
6L  
A
7L  
A
8L  
5R  
7C132  
A
0L  
A
6R  
13 7C142  
36  
35  
34  
A
A
14  
15  
16  
17  
18  
7R  
A
9L  
8R  
I/O  
I/O  
A
9R  
0L  
1L  
33  
32  
I/O  
ARBITRATION  
LOGIC  
(7C132/7C136 ONLY)  
AND  
INTERRUPTLOGIC  
(7C136/7C146 ONLY)  
7R  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
31  
30  
29  
28  
27  
26  
25  
2L  
3L  
6R  
5R  
4R  
3R  
2R  
19  
20  
21  
22  
23  
24  
CE  
L
I/O  
I/O  
CE  
R
4L  
5L  
OE  
L
OE  
R
I/O  
I/O  
6L  
7L  
R/W  
L
R/W  
R
I/O  
I/O  
1R  
0R  
GND  
[2]  
[2]  
INT  
L
INT  
R
C132-2  
C132-1  
Notes:  
1. CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor.  
CY7C142/CY7C146 (Slave): BUSY is input.  
2. Open drain outputs; pull-up resistor required.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
December 1989 – Revised March 27, 1997  
1234567...18

中文翻译

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 		x8 Dual-Port SRAM
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CY7C146-35JC CYPRESS

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