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CY7C1463AV25-133AXCT

更新时间： 2024-11-16 13:07:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	460K
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CY7C1461AV25

CY7C1463AV25

CY7C1465AV25

36-Mbit (1M x 36/2M x 18/512K x 72)

Flow-Through SRAM with NoBL™ Architecture

Functional Description^[1]

Features

• No Bus Latency™ (NoBL™) architecture eliminates

dead cycles between write and read cycles

The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 are

2.5V, 1M × 36/2M × 18/512K × 72 Synchronous Flow-through

Burst SRAMs designed specifically to support unlimited true

back-to-back Read/Write operations without the insertion of

• Can support up to 133-MHz bus operations with zero

wait states

wait

states.

The

CY7C1461AV25/CY7C1463AV25/

— Data is transferred on every clock

CY7C1465AV25 is equipped with the advanced No Bus

Latency (NoBL) logic required to enable consecutive

Read/Write operations with data being transferred on every

clock cycle. This feature dramatically improves the throughput

of data through the SRAM, especially in systems that require

frequent Write-Read transitions.

• Pin-compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

• 2.5V/1.8V I/O power supply

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

Write operations are controlled by the two or four Byte Write

Select (BW_X) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

• Clock Enable (CEN) pin to enable clock and suspend

operation

• Synchronous self-timed writes

• Asynchronous Output Enable

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

• CY7C1461AV25, CY7C1463AV25 available in

JEDEC-standard lead-free 100-pin TQFP package,

lead-free and non-lead-free 165-ball FBGA package.

CY7C1465AV25 available in lead-free and non-lead-free

209-ball FBGA package.

• Three chip enables for simple depth expansion

• Automatic Power-down feature available using ZZ

mode or CE deselect

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst Capability—linear or interleaved burst order

• Low standby power

Selection Guide

133 MHz

6.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

270

250

120

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05355 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 22, 2006

12 3 4 5 6 7...29

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与CY7C1463AV25-133AXCT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1463AV25-133AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Thro
CY7C1463AV25-133BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Thro
CY7C1463AV25-133BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Thro
CY7C1463AV25-133BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Thro
CY7C1463AV25-133BZXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Thro
CY7C1463AV33	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1463AV33-100AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1463AV33-100AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1463AV33-100BGC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 8.5ns, CMOS, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209
CY7C1463AV33-100BGXC	CYPRESS	获取价格	暂无描述

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