Datasheet > CY7C1463V25

CY7C1463V25

更新时间： 2024-11-15 23:45:31

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
34页	1097K
描述
Memory

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数据手册

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CY7C1463V25 数据手册

380B

CY7C1380B

CY7C1382B

512K x 36/1M x 18 Pipelined SRAM

isters controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE), burst control in-

puts (ADSC, ADSP, and ADV), write enables (BWa, BWb,

BWc, BWd and BWE), and Global Write (GW).

Features

• Fast clock speed: 200, 167, 150, 133 MHz

• Provide high-performance 3-1-1-1 access rate

• Fast OE access times: 3.0, 3.4, 3.8, and 4.2 ns

• Optimal for depth expansion

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). DQ_a,b,c,dand DP_a,b,c,dapply to

CY7C1380B and DQ_a,band DP_a,bapply to CY7C1382B. a, b,

c, d each are 8 bits wide in the case of DQ and 1 bit wide in

the case of DP.

• 3.3V (–5% / +10%) power supply

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Chip enable for address pipeline

• Address, data, and control registers

• Internally self-timed Write Cycle

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address Status Controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance Pin (ADV).

• Burst control pins (interleaved or linear burst se-

quence)

• Automatic power-down available using ZZ mode or CE

deselect

Address, data inputs, and write controls are registered on-chip

to initiate self-timed WRITE cycle. WRITE cycles can be one

to four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BWa

• High-density, high-speed packages

controls DQa and DPa. BWb controls DQ and DP . BWc con-

• JTAG boundary scan for BGA packaging version

trols DQc and DPc. BWd controls DQd and DPd. BWa, BWb,

BWc, and BWd can be active only with BWE being LOW. GW

being LOW causes all bytes to be written. WRITE

pass-through capability allows written data available at the out-

put for the immediately next READ cycle. This device also in-

corporates pipelined enable circuit for easy depth expansion

without penalizing system performance.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced sin-

gle-layer polysilicon, triple-layer metal technology. Each mem-

ory cell consists of six transistors.

The CY7C1380B and CY7C1382B SRAMs integrate

524,288x36 and 1,048,576x18 SRAM cells with advanced

synchronous peripheral circuitry and a 2-bit counter for inter-

nal burst operation. All synchronous inputs are gated by reg-

All inputs and outputs of the CY7C1380B and the CY7C1382B

are JEDEC standard JESD8-5 compatible.

Selection Guide

200 MHz

167 MHz

3.4

150 MHz

3.8

133 MHz

4.2

Maximum Access Time (ns)

3.0

315

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Commercial

285

265

245

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

October 8, 2001

12 3 4 5 6 7...34

中文翻译

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与CY7C1463V25相关器件

型号	品牌	获取价格	描述	数据表
CY7C1463V25-117BGC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1463V25-117BZC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 7.5ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1463V25-133BZC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1463V25-150BZC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 5.5ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1463V33	ETC	获取价格	Memory
CY7C1463V33-117AC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1463V33-117BGC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1463V33-117BZC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 7.5ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1463V33-133BGC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1463V33-133BZC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165

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