Datasheet > CY7C1463V33-133BZC

CY7C1463V33-133BZC

更新时间： 2024-11-16 15:43:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
26页	472K
描述
ZBT SRAM, 2MX18, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165

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CY7C1463V33-133BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	15 X 17 MM, 1.20 MM HEIGHT, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
Base Number Matches：	1

CY7C1463V33-133BZC 数据手册

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CY7C1461V33

CY7C1463V33

CY7C1465V33

PRELIMINARY

1Mx36/2Mx18/512Kx72Flow-ThruSRAM

with NoBL™ Architecture

BWS_c,BWS_d,BWS_e, BWS_f, BWS_g, BWS_h), and Read-Write

control (WE). BWS_cand BWS_dapply to CY7C1461V33 and

CY7C1465V33 only. BWS_e, BWS_f,BWS_gand BWS_happly to

CY7C1465V33 only

Features

• Zero Bus Latency , no dead cycles between Write and

Read cycles

•Supports 133-MHz bus operations

•1M × 36/2M × 18/512K × 72 common I/O

•Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

— 7.5 ns (for 117-MHz device)

Clock Enable (CEN) pin allows operation of the

CY7C1461V33, CY7C1463V33, and CY7C1465V33 to be

suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers

will hold their previous values.

There are three Chip Enable (CE₁, CE₂, CE₃) pins that allow

the user to deselect the device when desired. If any one of

these three are not active when ADV/LD is low, no new

memory operation can be initiated and any burst cycle in

progress is stopped. However, any pending data transfers

(READ or WRITE) will be completed. The data bus will be in

high impedance state two cycles after chip is deselected or a

Write cycle is initiated.

• Single 3.3V –5% and +5% power supply V_DD

• Separate V_DDQfor 3.3V or 2.5V

• Clock Enable (CEN) pin to suspend operation

• Burst Capability–linear or interleaved burst order

• Available in 119-ball bump BGA, 165-ball FBGA, and

100-pin TQFP packages (CY7C1461V33 and

CY7C1463V33). 209-ball FBGA package for

CY7C1465V33.

The CY7C1461V33, CY7C1463V33 and CY7C1465V33 have

an on-chip two-bit burst counter. In the burst mode,

CY7C1461V33, CY7C1463V33 and CY7C1465V33 provide

four cycles of data for a single address presented to the

SRAM. The order of the burst sequence is defined by the

MODE input pin. The MODE pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load

a new external address (ADV/LD = LOW) or increment the

internal burst counter (ADV/LD = HIGH)

Functional Description

The CY7C1461V33, CY7C1463V33 and CY7C1465V33

SRAMs are designed to eliminate dead cycles when transi-

tions from Read to Write or vice versa. These SRAMs are

optimized for 100% bus utilization and achieve Zero Bus

Latency. They integrate 1,048,576 × 36/2,097,152 × 18/

524,288 × 72 SRAM cells, respectively, with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. The Synchronous Burst SRAM family

employs high-speed, low-power CMOS designs using

advanced single layer polysilicon, threelayer metal

technology. Each memory cell consists of six transistors.

Output Enable (OE) and burst sequence select (MODE) are

the asynchronous signals. OE can be used to disable the

outputs at any given time. ZZ may be tied to LOW if it is not

used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE₁, CE₂and CE₃), cycle start input (ADV/LD),

Clock Enable (CEN), Byte Write Selects (BWS_a, BWS_b,

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

CEN

CONTROL

and WRITE

LOGIC

1M × 36

2M × 18

512K × 72

Memory

Array

BWS

X = a, b

, c, d

X= a, b,

c, d

X = a, b,

c, d

X = 19:0

X = 20:0

1M×36

Mode

X = a, b

X = a, b X = a, b

2M×18

X = a, b

X = a, b,

c,d,e,f,g,h

X = 18:0

512K×72

c,d,e,f,g,h

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05193 Rev. *B

Revised November 18, 2002

12 3 4 5 6 7...26

中文翻译

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与CY7C1463V33-133BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1463V33-150BGC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 5.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1463V33-150BZC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 5.5ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165
CY7C146-45JC	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM
CY7C146-45JCR	CYPRESS	获取价格	Multi-Port SRAM, 2KX8, 45ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C146-45JCT	CYPRESS	获取价格	Dual-Port SRAM, 2KX8, 45ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C146-45JI	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM
CY7C146-45JIR	CYPRESS	获取价格	暂无描述
CY7C146-45JIT	CYPRESS	获取价格	Dual-Port SRAM, 2KX8, 45ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C146-45LC	CYPRESS	获取价格	Multi-Port SRAM, 2KX8, 45ns, CMOS, CQCC52, CERAMIC, LCC-52
CY7C146-45LMB	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM

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