5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> CY7C146-45JIT
CY7C146-45JIT PDF预览

CY7C146-45JIT

更新时间： 2024-11-16 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
18页 564K
描述
Dual-Port SRAM, 2KX8, 45ns, CMOS, PQCC52, PLASTIC, LCC-52

阅读下载

中文翻译

获取价格

CY7C146-45JIT 技术参数

生命周期：Obsolete零件包装代码：LCC
包装说明：QCCJ,针数：52
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.75
最长访问时间：45 ns其他特性：AUTOMATIC POWER-DOWN; INTERRUPT FLAG
JESD-30 代码：S-PQCC-J52长度：19.1262 mm
内存密度：16384 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：8功能数量：1
端口数量：2端子数量：52
字数：2048 words字数代码：2000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：2KX8
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：5.08 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：19.1262 mmBase Number Matches：1

CY7C146-45JIT 数据手册

 浏览型号CY7C146-45JIT的Datasheet PDF文件第2页浏览型号CY7C146-45JIT的Datasheet PDF文件第3页浏览型号CY7C146-45JIT的Datasheet PDF文件第4页浏览型号CY7C146-45JIT的Datasheet PDF文件第5页浏览型号CY7C146-45JIT的Datasheet PDF文件第6页浏览型号CY7C146-45JIT的Datasheet PDF文件第7页 
CY7C132/CY7C136  
CY7C142/CY7C146  
2K x 8 Dual-Port Static RAM  
Features  
Functional Description  
• True Dual-Ported memory cells which allow simulta-  
neous reads of the same memory location  
The CY7C132/CY7C136/CY7C142 and CY7C146 are  
high-speed CMOS 2K by 8 dual-port static RAMs. Two ports  
are provided to permit independent access to any location in  
memory. The CY7C132/ CY7C136 can be utilized as either a  
standalone 8-bit dual-port static RAM or as a MASTER  
dual-port RAM in conjunction with the CY7C142/CY7C146  
SLAVE dual-port device in systems requiring 16-bit or greater  
word widths. It is the solution to applications requiring shared  
or buffered data such as cache memory for DSP, bit-slice, or  
multiprocessor designs.  
• 2K x 8 organization  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 15 ns  
• Low operating power: ICC = 110 mA (max.)  
• Fully asynchronous operation  
• Automatic power-down  
Each port has independent control pins; chip enable (CE),  
write enable (R/W), and output enable (OE). BUSY flags are  
provided on each port. In addition, an interrupt flag (INT) is  
provided on each port of the 52-pin PLCC version. BUSY  
signals that the port is trying to access the same location  
currently being accessed by the other port. On the PLCC  
version, INT is an interrupt flag indicating that data has been  
placed in a unique location (7FF for the left port and 7FE for  
the right port).  
• Master CY7C132/CY7C136 easily expands data bus  
width to 16 or more bits using slave CY7C142/CY7C146  
• BUSY output flag on CY7C132/CY7C136; BUSY input  
on CY7C142/CY7C146  
• INT flag for port-to-port communication (52-pin  
PLCC/PQFP versions)  
• Availablein48-pinDIP(CY7C132/142),52-pinPLCCand  
52-pin TQFP (CY7C136/146)  
An automatic power-down feature is controlled independently  
on each port by the chip enable (CE) pins.  
• Pb-Free packages available  
The CY7C132/CY7C142 are available in 48-pin DIP. The  
CY7C136/CY7C146 are available in 52-pin PLCC and PQFP.  
Logic Block Diagram  
Pin Configuration  
R/W  
L
R/W  
R
DIP  
CE  
L
CE  
R
Top View  
OE  
L
OE  
R
V
48  
1
CE  
L
CC  
CE  
R/W  
R
R/W  
BUSY  
47  
L
R
2
46  
3
L
BUSY  
45  
A
10L  
R
4
A
44  
5
I/O  
I/O  
OE  
10R  
OE  
I/O  
I/O  
7L  
L
7R  
I/O  
CONTROL  
I/O  
CONTROL  
A
0L  
43  
R
6
42  
7
A
0R  
0R  
A
1L  
A
2L  
A
3L  
0L  
[1]  
A
1R  
A
2R  
41  
[1]  
8
BUSY  
BUSY  
R
L
40  
9
A
A
A
39  
10  
3R  
4L  
5L  
A
A
A
10L  
10R  
0R  
MEMORY  
ARRAY  
A
4R  
A
5R  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
38  
37  
11  
12  
A
6L  
A
7L  
A
8L  
7C132  
A
0L  
A
6R  
13 7C142  
36  
35  
34  
A
7R  
A
8R  
14  
15  
16  
17  
18  
A
9L  
I/O  
0L  
I/O  
1L  
A
9R  
33  
32  
I/O  
ARBITRATION  
LOGIC  
(7C132/7C136 ONLY)  
AND  
INTERRUPTLOGIC  
(7C136/7C146 ONLY)  
7R  
I/O  
2L  
I/O  
3L  
I/O  
I/O  
I/O  
I/O  
I/O  
31  
30  
29  
28  
27  
26  
25  
6R  
5R  
4R  
3R  
2R  
19  
20  
21  
22  
23  
24  
CE  
L
I/O  
4L  
I/O  
5L  
CE  
R
OE  
L
OE  
R
I/O  
I/O  
6L  
R/W  
L
R/W  
R
I/O  
I/O  
1R  
7L  
GND  
0R  
[2]  
[2]  
INT  
INT  
R
L
Notes:  
1. CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor.  
CY7C142/CY7C146 (Slave): BUSY is input.  
2. Open drain outputs; pull-up resistor required.  
Cypress Semiconductor Corporation  
Document #: 38-06031 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 1, 2005  
1234567...18

中文翻译

下载PDF

与CY7C146-45JIT相关器件

型号 品牌 获取价格 描述 数据表
CY7C146-45LC CYPRESS

获取价格

 		Multi-Port SRAM, 2KX8, 45ns, CMOS, CQCC52, CERAMIC, LCC-52
CY7C146-45LMB CYPRESS

获取价格

 		2Kx8 Dual-Port Static RAM
CY7C146-45LMBT CYPRESS

获取价格

 		Dual-Port SRAM, 2KX8, 45ns, CMOS, LCC-52
CY7C146-45NC CYPRESS

获取价格

 		2Kx8 Dual-Port Static RAM
CY7C146-45NCT CYPRESS

获取价格

 		Dual-Port SRAM, 2KX8, 45ns, CMOS, PQFP52, PLASTIC, QFP-52
CY7C1464AV25 CYPRESS

获取价格

 		36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1464AV25-167 CYPRESS

获取价格

 		36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1464AV25-167BGC CYPRESS

获取价格

 		36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1464AV25-167BGI CYPRESS

获取价格

 		36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1464AV25-167BGXC CYPRESS

获取价格

 		36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined

与CY7C146-45JIT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证