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CY7C1463KV33-133AXC PDF预览

CY7C1463KV33-133AXC

更新时间: 2024-11-17 17:00:39
品牌 Logo 应用领域
英飞凌 - INFINEON 静态存储器
页数 文件大小 规格书
23页 2198K
描述
Synchronous SRAM

CY7C1463KV33-133AXC 数据手册

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CY7C1461KV33  
CY7C1463KV33  
36-Mbit (1M × 36/2M × 18) Flow-Through SRAM  
with NoBL™ Architecture  
36-Mbit (1M  
× 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture  
Features  
Functional Description  
No Bus Latency™ (NoBL™) architecture eliminates dead  
cycles between write and read cycles  
The  
CY7C1461KV33/CY7C1463KV33  
are  
3.3 V,  
1M × 36/2M × 18 Synchronous Flow-Through Burst SRAMs  
designed specifically to support unlimited true back-to-back read  
and write operations without the insertion of wait states. The  
CY7C1461KV33/CY7C1463KV33 is equipped with the advanced  
NoBL logic required to enable consecutive read and write  
operations with data being transferred on every clock cycle. This  
feature dramatically improves the throughput of data through the  
SRAM, especially in systems that require frequent write-read  
transitions.  
Supports up to 133 MHz bus operations with zero wait states  
Data is transferred on every clock  
Pin compatible and functionally equivalent to ZBT™ devices  
Internally self timed output buffer control to eliminate the need  
to use OE  
Registered inputs for flow through operation  
Byte write capability  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. The clock input is qualified by the  
Clock Enable (CEN) signal, which when deasserted suspends  
operation and extends the previous clock cycle. Maximum  
access delay from the clock rise is 6.5 ns (133 MHz device).  
3.3 V and 2.5 V I/O power supply  
Fast clock-to-output times  
6.5 ns (for 133-MHz device)  
Write operations are controlled by the two or four Byte Write  
Select (BWX) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self timed write circuitry.  
Clock Enable (CEN) pin to enable clock and suspend operation  
Synchronous self timed writes  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. To avoid bus contention,  
the output drivers are synchronously tri-stated during the data  
portion of a write sequence.  
Asynchronous Output Enable  
CY7C1461KV33,  
CY7C1463KV33  
available  
in  
JEDEC-standard Pb-free 100-pin TQFP packages  
Three chip enables for simple depth expansion  
Automatic power down feature available using ZZ mode or CE  
deselect  
Burst capability – linear or interleaved burst order  
Low standby power  
Selection Guide  
Description  
Maximum access time  
133 MHz  
6.5  
Unit  
ns  
Maximum operating current  
× 18  
× 36  
150  
mA  
170  
Cypress Semiconductor Corporation  
Document Number: 001-66681 Rev. *G  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 7, 2016  

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