Datasheet > CY7C1462V33-200AC

CY7C1462V33-200AC

更新时间： 2024-11-16 14:35:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
26页	478K
描述
ZBT SRAM, 2MX18, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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技术参数
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CY7C1462V33-200AC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：	100	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.92	Is Samacsys：	N
最长访问时间：	3 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	200 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	37748736 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	2097152 words
字数代码：	2000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	2MX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最小待机电流：	3.14 V	子类别：	SRAMs
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

CY7C1462V33-200AC 数据手册

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CY7C1460V33

CY7C1462V33

CY7C1464V33

PRELIMINARY

1M x 36/2M x 18/512K x 72 Pipelined SRAM

with NoBL™ Architecture

Clock Enable (CEN), Byte Write Selects (BWS_a, BWS_b, BWS_c

,BWS_d,BWS_e, BWS_f, BWS_g,BWS_h), and read-write control

(WE). BWS_cand BWS_dapply to CY7C1460V33 and

CY7C1464V33 only. BWS_e, BWS_f, BWS_g, and BWS_happly to

CY7C1464V33 only.

Features

• Zero Bus Latency , no dead cycles between write and

read cycles

• Fast clock speed: 250, 200, and 167 MHz

• Fast access time: 2.7, 3.0 and 3.5 ns

• Internally synchronized registered outputs eliminate

the need to control OE

• Single 3.3V –5% and +5% power supply V_DD

• Separate V_DDQfor 3.3V or 2.5V

• Single WE (Read/Write) control pin

• Positive clock-edge triggered, address, data, and

control signal registers for fully pipelined applications

• Interleaved or linear four-word burst capability

• Individual byte write (BWS_a– BWS_h) control (may be

tied LOW)

• CEN pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• JTAG boundary scan for BGA packaging version

• Available in 119-ball bump BGA, 165-ball FBGA

package and 100-pin TQFP packages (CY7C1460 and

CY7C1462). 209 FBGA package for CY7C1464.

Address and control signals are applied to the SRAM during

one clock cycle, and two cycles later, its associated data

occurs, either read or write.

Clock Enable (CEN) pin allows operation of the

CY7C1460V33, CY7C1462V33, and CY7C1464V33 to be

suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers

will hold their previous values.

There are three Chip Enable (CE₁, CE₂, CE₃) pins that allow

the user to deselect the device when desired. If any one of

these three are not active when ADV/LD is low, no new

memory operation can be initiated and any burst cycle in

progress is stopped. However, any pending data transfers

(read or write) will be completed. The data bus will be in high

impedance state two cycles after chip is deselected or a write

cycle is initiated.

The CY7C1460V33, CY7C1462V33, and CY7C1464V33

have an on-chip two-bit burst counter. In the burst mode,

CY7C1460V33, CY7C1462V33, and CY7C1464V33 provide

four cycles of data for a single address presented to the

SRAM. The order of the burst sequence is defined by the

MODE input pin. The MODE pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load

a new external address (ADV/LD = LOW) or increment the

internal burst counter (ADV/LD = HIGH).

Functional Description

The CY7C1460V33, CY7C1462V33, and CY7C1464V33

SRAMs are designed to eliminate dead cycles when transi-

tions from READ to WRITE or vice versa. These SRAMs are

optimized for 100 percent bus utilization and achieves Zero

Bus Latency. They integrate 1,048,576 x 36/2,097,152 x 18/

524,288 x 72 SRAM cells, respectively, with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. The Synchronous Burst SRAM family

employs high-speed, low-power CMOS designs using

advanced single-layer polysilicon, three-layer metal

technology. Each memory cell consists of six transistors.

Output Enable (OE) and burst sequence select (MODE) are

the asynchronous signals. OE can be used to disable the

outputs at any given time. ZZ may be tied to LOW if it is not

used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE₁, CE₂, and CE₃), cycle start input (ADV/LD),

CLK

Data-In REG.

Logic Block Diagram

ADV/LD

CEN

CONTROL

and WRITE

LOGIC

1Mx36

2Mx18

BWS

512Kx72

X = a, b

, c, d

X = a, b, X= a, b,

c, d

MEMORY

ARRAY

X = 19:0

X = 20:0

1Mx36

c, d

BWS

X = a, b

X = a, b X = a, b

Mode

2Mx18

X = a, b

X = a, b,

X = 18:0

512Kx72

c,d,e,f,g,h

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05190 Rev. *C

Revised November 14, 2002

12 3 4 5 6 7...26

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与CY7C1462V33-200AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1462V33-250BGC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 2.7ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1462V33-250BZC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 2.7ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1462V33-300AC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 2.3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1462V33-300BGC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 2.3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1462V33-300BZC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 2.3ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165
CY7C146-30JC	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM
CY7C146-30JCR	CYPRESS	获取价格	Multi-Port SRAM, 2KX8, 30ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C146-30JI	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM
CY7C146-30JIR	CYPRESS	获取价格	Multi-Port SRAM, 2KX8, 30ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C146-30JIT	CYPRESS	获取价格	Dual-Port SRAM, 2KX8, 30ns, CMOS, PQCC52, PLASTIC, LCC-52

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