Datasheet > CY7C1462KVE25-167BZI

CY7C1462KVE25-167BZI

更新时间： 2024-11-17 14:56:15

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
24页	676K
描述
Synchronous SRAM with ECC

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CY7C1371KV33

CY7C1371KVE33

CY7C1373KV33

18-Mbit (512K × 36/1M × 18)

Flow-Through SRAM

with NoBL™ Architecture (With ECC)

18-Mbit (512K

× 36/1M × 18) Flow-through SRAM with NoBL™ Architecture (With ECC)

Features

Functional Description

■ No Bus Latency (NoBL) architecture eliminates dead cycles

The CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 are

3.3 V, 512K × 36/1M × 18 synchronous flow through burst SRAM

designed specifically to support unlimited true back-to-back

read/write operations with no wait state insertion. The

between write and read cycles

■ Supports up to 133 MHz bus operations with zero wait states

❐ Data is transferred on every clock

CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33

are

equipped with the advanced No Bus Latency (NoBL) logic

required to enable consecutive read/write operations with data

being transferred on every clock cycle. This feature dramatically

improves the throughput of data through the SRAM, especially

in systems that require frequent write-read transitions.

■ Pin-compatible and functionally equivalent to ZBT™ devices

■ Internally self-timed output buffer control to eliminate the need

to use OE

■ Registered inputs for flow through operation

■ Byte write capability

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock input is qualified by the

clock enable (CEN) signal, which when deasserted suspends

operation and extends the previous clock cycle. Maximum

access delay from the clock rise is 6.5 ns (133 MHz device).

■ 3.3 V/2.5 V I/O power supply (V_DDQ

)

■ Fast clock-to-output times

❐ 6.5 ns (for 133 MHz device)

Write operations are controlled by the two or four byte write

select (BW_X) and a write enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

■ Clock enable (CEN) pin to enable clock and suspend operation

■ Synchronous self-timed writes

Three synchronous chip enables (CE₁, CE₂, CE₃) and an

asynchronous output enable (OE) provide for easy bank

selection and output tristate control. To avoid bus contention, the

output drivers are synchronously tristated during the data portion

of a write sequence.

■ Asynchronous output enable

■ Available in JEDEC-standard Pb-free 100-pin TQFP packages

■ Three chip enables for simple depth expansion

■ Automatic power-down feature available using ZZ mode or CE

deselect

■ Burst capability – linear or interleaved burst order

■ Low standby power

■ On chip Error Correction Code (ECC) to reduce Soft Error Rate

(SER)

Selection Guide

Description

Maximum access time

133 MHz

6.5

100 MHz Unit

8.5

114

134

Maximum operating current

× 18

× 36

129

149

Cypress Semiconductor Corporation

Document Number: 001-97852 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 8, 2018

12 3 4 5 6 7...24

中文翻译

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与CY7C1462KVE25-167BZI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1462KVE33	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Pipelined SRAM wi
CY7C1462KVE33-167AXC	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Pipelined SRAM wi
CY7C1462KVE33-167AXC	INFINEON	获取价格	Synchronous SRAM with ECC
CY7C1462V25	ETC	获取价格	Memory
CY7C1462V25-167AC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1462V25-167BGC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1462V25-167BZC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 3.5ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1462V25-200BZC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 3ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1462V25-250AC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 2.7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1462V25-250BGC	CYPRESS	获取价格	ZBT SRAM, 2MX18, 2.7ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

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