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CY7C1441KV33-133AXI PDF预览

CY7C1441KV33-133AXI

更新时间： 2024-10-26 19:57:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
32页 2969K
描述
Standard SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100

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CY7C1441KV33-133AXI 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：LQFP,Reach Compliance Code：compliant
ECCN代码：3A991HTS代码：8542.32.00.41
风险等级：2.29最长访问时间：6.5 ns
JESD-30 代码：R-PQFP-G100长度：20 mm
内存密度：37748736 bit内存集成电路类型：STANDARD SRAM
内存宽度：36功能数量：1
端子数量：100字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX36封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

CY7C1441KV33-133AXI 数据手册

 浏览型号CY7C1441KV33-133AXI的Datasheet PDF文件第2页浏览型号CY7C1441KV33-133AXI的Datasheet PDF文件第3页浏览型号CY7C1441KV33-133AXI的Datasheet PDF文件第4页浏览型号CY7C1441KV33-133AXI的Datasheet PDF文件第5页浏览型号CY7C1441KV33-133AXI的Datasheet PDF文件第6页浏览型号CY7C1441KV33-133AXI的Datasheet PDF文件第7页 
CY7C1441KV33  
CY7C1443KV33  
CY7C1441KVE33  
36-Mbit (1M × 36/2M × 18) Flow-Through  
SRAM (With ECC)  
36-Mbit (1M  
× 36/2M × 18) Flow-Through SRAM (With ECC)  
Features  
Functional Description  
■ Supports 133-MHz bus operations  
■ 1M × 36/2M × 18 common I/O  
■ 3.3 V core power supply  
The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 are  
3.3 V, 1M × 36/2M × 18/1M × 36 synchronous flow-through  
SRAMs, respectively designed to interface with high-speed  
microprocessors with minimum glue logic. Maximum access  
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip  
counter captures the first address in a burst and increments the  
address automatically for the rest of the burst access. All  
synchronous inputs are gated by registers controlled by a  
positive-edge-triggered Clock (CLK) input. The synchronous  
inputs include all addresses, all data inputs, address-pipelining  
Chip Enable (CE1), depth-expansion Chip Enables (CE2 and  
CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write  
Enables (BWx, and BWE), and Global Write (GW).  
Asynchronous inputs include the Output Enable (OE) and the ZZ  
pin.  
■ 2.5 V or 3.3 V I/O power supply  
■ Fast clock-to-output times  
❐ 6.5 ns (133 MHz version)  
■ Provide high-performance 2-1-1-1 access rate  
■ User-selectable burst counter supporting IntelPentium  
interleaved or linear burst sequences  
■ Separate processor and controller address strobes  
■ Synchronous self-timed write  
■ Asynchronous output enable  
CY7C1441KVE33  
The CY7C1441KV33/CY7C1443KV33/  
allow  
either interleaved or linear burst sequences, selected by the  
MODE input pin. A HIGH selects an interleaved burst sequence,  
while a LOW selects a linear burst sequence. Burst accesses  
can be initiated with the Processor Address Strobe (ADSP) or the  
cache Controller Address Strobe (ADSC) inputs. Address  
advancement is controlled by the Address Advancement (ADV)  
input.  
■ CY7C1441KV33, CY7C1443KV33, and CY7C1441KVE33 are  
available in JEDEC-standard 100-pin TQFP and 165-ball  
FBGA Pb-free packages.  
■ IEEE 1149.1 JTAG-Compatible Boundary Scan  
■ “ZZ” Sleep Mode option  
■ On-chip error correction code (ECC) to reduce soft error rate  
(SER)  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or Address  
Strobe Controller (ADSC) are active. Subsequent burst  
addresses can be internally generated as controlled by the  
Advance pin (ADV).  
The  
CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33  
operate from a +3.3 V core power supply while all outputs may  
operate with either a +2.5 V or +3.3 V supply. All inputs and  
outputs are JEDEC-standard JESD8-5-compatible.  
Selection Guide  
Description  
Maximum access time  
133 MHz  
6.5  
Unit  
ns  
Maximum operating current  
× 18  
× 36  
150  
mA  
170  
Cypress Semiconductor Corporation  
Document Number: 001-66677 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 5, 2016  
 
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CY7C1441KV33-133AXI 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1441AV33-133AXI CYPRESS

完全替代

 36-Mbit (1 M x 36/2 M x 18/512 k x 72) Flow-Through SRAM
CY7C1441AV33-133AXIT CYPRESS

类似代替

 Standard SRAM, 1MX36, 6.5ns, CMOS, PQFP100

与CY7C1441KV33-133AXI相关器件

型号 品牌 获取价格 描述 数据表
CY7C1441KV33-133AXM CYPRESS

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 		Cache SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1441KV33-133AXM INFINEON

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 		Synchronous SRAM
CY7C1441KV33-133BZM INFINEON

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 		Synchronous SRAM
CY7C1441KV33-133BZXI CYPRESS

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 		36-Mbit (1M × 36/2M × 18) Flow-Through SRAM
CY7C1441KVE33 CYPRESS

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 		36-Mbit (1M × 36/2M × 18) Flow-Through SRAM
CY7C1441KVE33-133AXC CYPRESS

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 		36-Mbit (1M × 36/2M × 18) Flow-Through SRAM
CY7C1441KVE33-133AXC INFINEON

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 		Synchronous SRAM with ECC
CY7C1441KVE33-133AXI INFINEON

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 		Synchronous SRAM with ECC
CY7C1441V25-133BGC CYPRESS

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 		Standard SRAM, 1MX36, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1441V25-133BZC CYPRESS

获取价格

 		Standard SRAM, 1MX36, 6.5ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165

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