Datasheet > CY7C1441KV33-133AXM

CY7C1441KV33-133AXM

更新时间： 2024-11-21 14:56:19

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
31页	926K
描述
Synchronous SRAM

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CY7C1441KV33

Military Temperature, 36-Mbit (1M × 36)

Flow-Through SRAM

Military Temperature, 36-Mbit (1M

× 36) Flow-Through SRAM

Features

Functional Description

■ Supports 133 MHz bus operations

■ 1M × 36 common I/O

The CY7C1441KV33 is 3.3 V, 1M × 36 synchronous

flow-through SRAMs, respectively designed to interface with

high-speed microprocessors with minimum glue logic. Maximum

access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit

on-chip counter captures the first address in a burst and

increments the address automatically for the rest of the burst

access. All synchronous inputs are gated by registers controlled

■ 3.3 V core power supply

■ 2.5 V or 3.3 V I/O power supply

■ Fast clock-to-output times

❐ 6.5 ns (133 MHz version)

positive-edge-triggered Clock (CLK) input. The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE₁), depth-expansion Chip

Enables (CE₂and CE₃), Burst Control inputs (ADSC, ADSP, and

ADV), Write Enables (BW_x, and BWE), and Global Write (GW).

Asynchronous inputs include the Output Enable (OE) and the ZZ

pin.

■ Provide high-performance 2-1-1-1 access rate

■ User-selectable burst counter supporting interleaved or linear

burst sequences

■ Separate processor and controller address strobes

■ Synchronous self-timed write

The CY7C1441KV33 allows either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects an

interleaved burst sequence, while a LOW selects a linear burst

sequence. Burst accesses can be initiated with the Processor

Address Strobe (ADSP) or the cache Controller Address Strobe

(ADSC) inputs. Address advancement is controlled by the

Address Advancement (ADV) input.

■ Asynchronous output enable

■ CY7C1441KV33 is available in JEDEC-standard 100-pin

TQFP and 165-ball FBGA Pb-free packages.

■ IEEE 1149.1 JTAG-Compatible Boundary Scan

■ “ZZ” Sleep Mode option

■ Available in Military Temperature Range

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or Address

Strobe Controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

Advance pin (ADV).

The CY7C1441KV33 operates from a +3.3 V core power supply

while all outputs may operate with either a +2.5 V or +3.3 V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

Description

Maximum access time

133 MHz

6.5

Unit

Maximum operating current

× 36

180

Cypress Semiconductor Corporation

Document Number: 002-12701 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 7, 2018

12 3 4 5 6 7...31

中文翻译

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与CY7C1441KV33-133AXM相关器件

型号	品牌	获取价格	描述	数据表
CY7C1441KV33-133BZM	INFINEON	获取价格	Synchronous SRAM
CY7C1441KV33-133BZXI	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Flow-Through SRAM
CY7C1441KVE33	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Flow-Through SRAM
CY7C1441KVE33-133AXC	CYPRESS	获取价格	36-Mbit (1M Ã 36/2M Ã 18) Flow-Through SRAM
CY7C1441KVE33-133AXC	INFINEON	获取价格	Synchronous SRAM with ECC
CY7C1441KVE33-133AXI	INFINEON	获取价格	Synchronous SRAM with ECC
CY7C1441V25-133BGC	CYPRESS	获取价格	Standard SRAM, 1MX36, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1441V25-133BZC	CYPRESS	获取价格	Standard SRAM, 1MX36, 6.5ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165
CY7C1441V25-150AC	CYPRESS	获取价格	Standard SRAM, 1MX36, 5.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1441V33	ETC	获取价格	Memory

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