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CY7C144-25JC PDF预览

CY7C144-25JC

更新时间： 2024-11-24 05:09:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
19页 391K
描述
8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy

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中文翻译

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CY7C144-25JC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：LCC包装说明：PLASTIC, LCC-68
针数：68Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.81最长访问时间：25 ns
其他特性：SEMAPHOREI/O 类型：COMMON
JESD-30 代码：S-PQCC-J68JESD-609代码：e0
长度：24.2316 mm内存密度：65536 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：8
功能数量：1端口数量：2
端子数量：68字数：8192 words
字数代码：8000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：8KX8输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC68,1.0SQ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
座面最大高度：5.08 mm最大待机电流：0.015 A
最小待机电流：4.5 V子类别：SRAMs
最大压摆率：0.18 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：24.2316 mmBase Number Matches：1

CY7C144-25JC 数据手册

 浏览型号CY7C144-25JC的Datasheet PDF文件第2页浏览型号CY7C144-25JC的Datasheet PDF文件第3页浏览型号CY7C144-25JC的Datasheet PDF文件第4页浏览型号CY7C144-25JC的Datasheet PDF文件第5页浏览型号CY7C144-25JC的Datasheet PDF文件第6页浏览型号CY7C144-25JC的Datasheet PDF文件第7页 
1CY7C144  
fax id: 5205  
CY7C145  
CY7C144  
8K x 8/9 Dual-Port Static RAM  
with Sem, Int, Busy  
are included on the CY7C144/5 to handle situations when mul-  
tiple processors access the same piece of data. Two ports are  
provided permitting independent, asynchronous access for  
reads and writes to any location in memory. The CY7C144/5  
can be utilized as a standalone 64/72-Kbit dual-port static  
RAM or multiple devices can be combined in order to function  
as a 16/18-bit or wider master/slave dual-port static RAM. An  
M/S pin is provided for implementing 16/18-bit or wider mem-  
ory applications without the need for separate master and  
slave devices or additional discrete logic. Application areas  
include interprocessor/multiprocessor designs, communica-  
tions status buffering, and dual-port video/graphics memory.  
Features  
• True Dual-Ported memory cells which allow  
simultaneous reads of the same memory location  
• 8K x 8 organization (CY7C144)  
• 8K x 9 organization (CY7C145)  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 15ns  
• Low operating power: I = 160 mA (max.)  
CC  
• Fully asynchronous operation  
• Automatic power-down  
• TTL compatible  
• Master/Slave select pin allows bus width expansion to  
16/18 bits or more  
• Busy arbitration scheme provided  
• Semaphores included to permit software handshaking  
between ports  
• INT flag for port-to-port communication  
• Available in 68-pin PLCC, 64-pin and 80-pin TQFP  
• Pin compatible and functionally equivalent to  
IDT7005/IDT7015  
Each port has independent control pins: chip enable (CE),  
read or write enable (R/W), and output enable (OE). Two flags,  
BUSYand INT, are provided on each port. BUSY signals that the port  
is trying to access the same location currently being accessed by the  
other port. The interrupt flag (INT) permits communication between  
ports or systems by means of a mail box. The semaphores are used  
to pass a flag, or token, from one port to the other to indicate that a  
shared resource is in use. The semaphore logic is comprised of eight  
shared latches. Only one side can control the latch (semaphore) at  
any time. Control of a semaphore indicates that a shared resource is  
in use. An automatic power-down feature is controlled independently  
on each port by a chip enable (CE) pin or SEM pin.  
Functional Description  
The CY7C144 and CY7C145 are high-speed CMOS 8K x 8  
and 8K x 9 dual-port static RAMs. Various arbitration schemes  
Logic Block Diagram  
R/W  
L
R/W  
R
CE  
OE  
CE  
OE  
L
L
R
R
(7C145) I/O  
I/O (7C145)  
8R  
8L  
I/O  
7L  
I/O  
7R  
I/O  
CONTROL  
I/O  
CONTROL  
I/O  
0L  
I/O  
0R  
[1, 2]  
[1, 2]  
BUSY  
BUSY  
L
R
A
12L  
0L  
A
A
12R  
0R  
MEMORY  
ARRAY  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
A
INTERRUPT  
SEMAPHORE  
ARBITRATION  
CE  
L
CE  
OE  
R
R
OE  
L
R/W  
R/W  
L
R
SEM  
L
SEM  
L
R
[2]  
[2]  
INT  
INT  
R
C144-1  
M/S  
Notes:  
1. BUSY is an output in master mode and an input in slave mode.  
2. Interrupt: push-pull output and requires no pull-up resistor.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
November 1996  
1234567...19

中文翻译

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CY7C144-25JC 替代型号

型号 品牌 替代类型 描述 数据表
IDT7005S25J IDT

功能相似

 HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
IDT7005L25J IDT

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 HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

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