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CY7C1442AV33-167AXI

更新时间： 2024-10-26 05:19:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	576K
描述
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

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CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

36-Mbit (1M x 36/2M x 18/512K x 72)

Pipelined Sync SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM

integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

• Available speed grades are 250, 200 and 167 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE₁), depth-expansion Chip Enables (CE₂and CE₃), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables (BW_X

and BWE), and Global Write (GW). Asynchronous inputs

include the Output Enable (OE) and the ZZ pin.

• 2.5V/3.3V I/O power supply

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the byte write control inputs. GW when active

• Single Cycle Chip Deselect

• CY7C1440AV33, CY7C1442AV33 available in lead-free

100-pin TQFP package, lead-free and non-lead-free

165-ball FBGA package. CY7C1446AV33 available in

lead-free and non-lead-free 209-ball FBGA package

causes all bytes to be written.

LOW

The

CY7C1440AV33/CY7C1442AV33/CY7C1446AV33

• Also available in lead-free packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

operates from a +3.3V core power supply while all outputs may

operate with either a +2.5 or +3.3V supply. All inputs and

outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide

250 MHz

2.6

200 MHz

3.2

167 MHz

3.4

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

475

425

375

120

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05383 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 23, 2006

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与CY7C1442AV33-167AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1442AV33-167BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1442AV33-167BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1442AV33-167BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1442AV33-167BZXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1442AV33-200AC	CYPRESS	获取价格	Cache SRAM, 2MX18, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1442AV33-200AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1442AV33-200AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1442AV33-200BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1442AV33-200BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1442AV33-200BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

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