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CY7C1442AV33-167BZC PDF预览

CY7C1442AV33-167BZC

更新时间： 2024-11-24 05:19:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
27页 392K
描述
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

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CY7C1442AV33-167BZC 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：BGA包装说明：17 X 15 MM, 1.4 MM HEIGHT, FBGA-165
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.92Is Samacsys：N
最长访问时间：3.4 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：167 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e0
长度：17 mm内存密度：37748736 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：2MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：220电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.4 mm
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.375 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：15 mmBase Number Matches：1

CY7C1442AV33-167BZC 数据手册

 浏览型号CY7C1442AV33-167BZC的Datasheet PDF文件第2页浏览型号CY7C1442AV33-167BZC的Datasheet PDF文件第3页浏览型号CY7C1442AV33-167BZC的Datasheet PDF文件第4页浏览型号CY7C1442AV33-167BZC的Datasheet PDF文件第5页浏览型号CY7C1442AV33-167BZC的Datasheet PDF文件第6页浏览型号CY7C1442AV33-167BZC的Datasheet PDF文件第7页 
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
PRELIMINARY  
36-Mbit (1M x 36/2M x 18/512K x 72)  
Pipelined Sync SRAM  
Features  
Functional Description[1]  
• Supports bus operation up to 250 MHz  
The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM  
integrates 1,048,576 x 36, 2,097,152 x 18 and 524,288 x 72  
SRAM cells with advanced synchronous peripheral circuitry  
• Available speed grades are 250, 200,167 MHz  
• Registered inputs and outputs for pipelined operation  
• 3.3V core power supply  
and a two-bit counter for internal burst operation. All  
synchronous inputs are gated by registers controlled by a  
positive-edge-triggered Clock Input (CLK). The synchronous  
inputs include all addresses, all data inputs, address-pipelining  
Chip Enable (CE1), depth-expansion Chip Enables (CE2 and  
CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write  
Enables (BWX and BWE), and Global Write (GW).  
Asynchronous inputs include the Output Enable (OE) and the  
ZZ pin.  
• 2.5V/3.3V I/O operation  
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
— 3.2 ns (for 200-MHz device)  
— 3.4 ns (for 167-MHz device)  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
• Provide high-performance 3-1-1-1 access rate  
• User-selectable burst counter supporting Intel®  
Pentium® interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to two or four bytes wide as  
controlled by the byte write control inputs. GW when active  
• Asynchronous output enable  
• Single Cycle Chip Deselect  
• Offered in JEDEC-standard 100-pin TQFP, 165-Ball  
fBGA and 209-Ball fBGA packages  
causes all bytes to be written.  
LOW  
The  
CY7C1440AV33/CY7C1442AV33/CY7C1446AV33  
• Also available in lead-free packages  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode Option  
operates from a +3.3V core power supply while all outputs may  
operate with either a +2.5 or +3.3V supply. All inputs and  
outputs are JEDEC-standard JESD8-5-compatible.  
Selection Guide  
250 MHz  
2.6  
200 MHz  
3.2  
167 MHz  
3.4  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
475  
425  
375  
mA  
mA  
100  
100  
100  
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.  
Notes:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE , CE are for TQFP and 165 fBGA package only.  
3
2
Cypress Semiconductor Corporation  
Document #: 38-05383 Rev. *B  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised January 31, 2005  
1234567...27

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 		36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
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 		36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1442AV33-200BZI CYPRESS

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 		36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1442AV33-200BZXC CYPRESS

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 		36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
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 		36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

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