Datasheet > CY7C144-35AIT

CY7C144-35AIT

更新时间： 2024-10-26 19:50:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
20页	651K
描述
Dual-Port SRAM, 8KX8, 35ns, CMOS, PQFP64, 14 X 14 MM, 1.4 MM HEIGHT, PLASTIC, TQFP-64

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技术参数
数据手册

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CY7C144-35AIT 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	64
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.41	风险等级：	5.76
最长访问时间：	35 ns	JESD-30 代码：	S-PQFP-G64
长度：	14 mm	内存密度：	65536 bit
内存集成电路类型：	DUAL-PORT SRAM	内存宽度：	8
功能数量：	1	端子数量：	64
字数：	8192 words	字数代码：	8000
工作模式：	ASYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	8KX8
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

CY7C144-35AIT 数据手册

CY7C144, CY7C145

8K x 8/9 Dual-Port Static RAM

with SEM, INT, BUSY

Features

Functional Description

■ True Dual-Ported Memory Cells that Enable Simultaneous

Reads of the same Memory Location

The CY7C144 and CY7C145 are high speed CMOS 8K x 8 and

8K x 9 dual-port static RAMs. Various arbitration schemes are

included on the CY7C144/5 to handle situations when multiple

processors access the same piece of data. Two ports are

provided permitting independent, asynchronous access for

reads and writes to any location in memory. The CY7C144/5 can

be used as a standalone 64/72-Kbit dual-port static RAM or

multiple devices can be combined in order to function as a

16/18-bit or wider master/slave dual-port static RAM. An M/S pin

is provided for implementing 16/18-bit or wider memory applica-

tions without the need for separate master and slave devices or

additional discrete logic. Application areas include interpro-

■ 8K x 8 Organization (CY7C144)

■ 8K x 9 Organization (CY7C145)

■ 0.65-Micron CMOS for optimum Speed and Power

■ High Speed Access: 15 ns

■ Low Operating Power: I_CC= 160 mA (max.)

■ Fully Asynchronous Operation

■ Automatic Power Down

cessor/multiprocessor

designs,

communications

status

buffering, and dual-port video/graphics memory.

■ TTL Compatible

Each port has independent control pins: chip enable (CE), read

or write enable (R/W), and output enable (OE). Two flags, BUSY

and INT, are provided on each port. BUSY signals that the port

is trying to access the same location currently being accessed

by the other port. The interrupt flag (INT) permits communication

between ports or systems by means of a mail box. The

semaphores are used to pass a flag, or token, from one port to

the other to indicate that a shared resource is in use. The

semaphore logic is comprised of eight shared latches. Only one

side can control the latch (semaphore) at any time. Control of a

semaphore indicates that a shared resource is in use. An

automatic power down feature is controlled independently on

each port by a chip enable (CE) pin or SEM pin.

■ Master/SlaveSelectPinenablesBusWidthExpansionto16/18

Bits or more

■ Busy Arbitration Scheme provided

■ Semaphores included to permit Software Handshaking

between Ports

■ INT Flag for Port-to-Port Communication

■ Available in 68-pin PLCC, 64-pin and 80-pin TQFP

■ Pb-free Packages available

R/W

Logic Block Diagram

(7C145) I/O

I/O (7C145)

I/O

CONTROL

I/O

CONTROL

I/O

[1, 2]

BUSY

12L

12R

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS

DECODER

INTERRUPT

SEMAPHORE

ARBITRATION

R/W

SEM

[2]

INT

INT [2]

M/S

Notes

1. BUSY is an output in master mode and an input in slave mode.

2. Interrupt: push-pull output and requires no pull-up resistor.

Cypress Semiconductor Corporation

Document #: 38-06034 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 26, 2009

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与CY7C144-35AIT相关器件

型号	品牌	获取价格	描述	数据表
CY7C144-35JC	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C144-35JCR	CYPRESS	获取价格	Dual-Port SRAM, 8KX8, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C144-35JCT	CYPRESS	获取价格	Dual-Port SRAM, 8KX8, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C144-35JCT	ROCHESTER	获取价格	8KX8 DUAL-PORT SRAM, 35ns, PQCC68, PLASTIC, LCC-68
CY7C144-35JI	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C144-35JIR	CYPRESS	获取价格	暂无描述
CY7C144-35JIT	CYPRESS	获取价格	Dual-Port SRAM, 8KX8, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C1443AV25	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
CY7C1443AV25-100AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
CY7C1443AV25-100AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM

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