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CY7C1443AV33-100AXI PDF预览

CY7C1443AV33-100AXI

更新时间： 2024-11-27 05:19:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
31页 567K
描述
36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM

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中文翻译

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CY7C1443AV33-100AXI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP, QFP100,.63X.87
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.84最长访问时间：8.5 ns
其他特性：FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：37748736 bit内存集成电路类型：CACHE SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：2097152 words字数代码：2000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：2MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最小待机电流：3.14 V
子类别：SRAMs最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：14 mmBase Number Matches：1

CY7C1443AV33-100AXI 数据手册

 浏览型号CY7C1443AV33-100AXI的Datasheet PDF文件第2页浏览型号CY7C1443AV33-100AXI的Datasheet PDF文件第3页浏览型号CY7C1443AV33-100AXI的Datasheet PDF文件第4页浏览型号CY7C1443AV33-100AXI的Datasheet PDF文件第5页浏览型号CY7C1443AV33-100AXI的Datasheet PDF文件第6页浏览型号CY7C1443AV33-100AXI的Datasheet PDF文件第7页 
CY7C1441AV33  
CY7C1443AV33  
CY7C1447AV33  
36-Mbit (1M x 36/2M x 18/512K x 72)  
Flow-Through SRAM  
Features  
Functional Description[1]  
• Supports 133-MHz bus operations  
• 1M x 36/2M x 18/512K x 72 common I/O  
• 3.3V core power supply  
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 are  
3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through  
SRAMs, respectively designed to interface with high-speed  
microprocessors with minimum glue logic. Maximum access  
delay from clock rise is 6.5 ns (133-MHz version). A 2-bit  
on-chip counter captures the first address in a burst and incre-  
ments the address automatically for the rest of the burst  
access. All synchronous inputs are gated by registers  
controlled by a positive-edge-triggered Clock Input (CLK). The  
synchronous inputs include all addresses, all data inputs,  
address-pipelining Chip Enable (CE1), depth-expansion Chip  
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP,  
• 2.5V or 3.3V I/O power supply  
• Fast clock-to-output times  
— 6.5 ns (133-MHz version)  
• Provide high-performance 2-1-1-1 access rate  
• User-selectable burst counter supporting Intel®  
Pentium® interleaved or linear burst sequences  
and ADV), Write Enables (BWx, and BWE), and Global Write  
(GW). Asynchronous inputs include the Output Enable (OE)  
and the ZZ pin.  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
• Asynchronous output enable  
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows  
either interleaved or linear burst sequences, selected by the  
MODE input pin. A HIGH selects an interleaved burst  
sequence, while a LOW selects a linear burst sequence. Burst  
accesses can be initiated with the Processor Address Strobe  
(ADSP) or the cache Controller Address Strobe (ADSC)  
inputs. Address advancement is controlled by the Address  
Advancement (ADV) input.  
• CY7C1441AV33, CY7C1443AV33 available in  
JEDEC-standard lead-free 100-pin TQFP package,  
lead-free and non-lead-free 165-ball FBGA package.  
CY7C1447AV33 available in lead-free and non-lead-free  
209-ball FBGA package  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode option  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
The  
CY7C1441AV33/CY7C1443AV33/CY7C1447AV33  
operates from a +3.3V core power supply while all outputs may  
operate with either a +2.5 or +3.3V supply. All inputs and  
outputs are JEDEC-standard JESD8-5-compatible.  
Selection Guide  
133 MHz  
6.5  
100 MHz  
8.5  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
310  
290  
mA  
mA  
120  
120  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05357 Rev. *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 23, 2006  
[+] Feedback  
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CY7C1443AV33-133BZI CYPRESS

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 		36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
CY7C1443AV33-133BZXC CYPRESS

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 		36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
CY7C1443AV33-133BZXI CYPRESS

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 		36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM

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