Datasheet > CY7C1442KV33

CY7C1442KV33

更新时间： 2024-11-25 01:14:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
33页	3076K
描述
36-Mbit (1M Ã 36/2M Ã 18) Pipelined Sync SRAM (With ECC)

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CY7C1442KV33 数据手册

CY7C1440KV33

CY7C1442KV33

CY7C1440KVE33

36-Mbit (1M × 36/2M × 18)

Pipelined Sync SRAM (With ECC)

36-Mbit (1M

× 36/2M × 18) Pipelined Sync SRAM (With ECC)

Features

Functional Description

■ Supports bus operation up to 250 MHz

■ Available speed grades are 250 MHz and 167 MHz

■ Registered inputs and outputs for pipelined operation

■ 3.3 V core power supply

The CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33 SRAM

integrate 1M × 36/2M × 18/1M × 36 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered clock input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining chip enable (CE₁), depth-expansion

chip enables (CE₂and CE₃), burst control inputs (ADSC, ADSP,

and ADV), write enables (BW_Xand BWE), and global write (GW).

Asynchronous inputs include the output enable (OE) and the ZZ

pin.

■ 2.5 V or 3.3 V I/O power supply

■ Fast clock-to-output time

❐ 2.5 ns (for 250 MHz device)

■ Provide high-performance 3-1-1-1 access rate

■ User-selectable burst counter supporting interleaved or linear

burst sequences

Addresses and chip enables are registered at rising edge of

clock when either address strobe processor (ADSP) or address

strobe controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

advance pin (ADV).

■ Separate processor and controller address strobes

■ Synchronous self-timed writes

■ Asynchronous output enable

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed write cycle. This part supports byte write

operations (see pin descriptions and truth table for further

details). Write cycles can be one, two or four bytes wide as

controlled by the byte write control inputs. GW when active LOW

causes all bytes to be written.

■ Single cycle chip deselect

■ CY7C1440KV33, CY7C1442KV33 and CY7C1440KVE33 are

availableinPb-free100-pinTQFP, andPb-freeandnonPb-free

165-ball FBGA packages.

■ IEEE 1149.1 JTAG-compatible boundary scan

■ “ZZ” sleep mode option

The

CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33

operate from a +3.3 V core power supply while all outputs may

operate with either a +2.5 V or +3.3 V supply. All inputs and

outputs are JEDEC-standard JESD8-5-compatible.

■ On-Chip error correction code (ECC) to reduce soft error rate

(SER)

Selection Guide

Description

Maximum access time

250 MHz

2.5

167 MHz Unit

3.4 ns

Maximum operating current

× 18

× 36

220

Not Offered mA

190

240

Cypress Semiconductor Corporation

Document Number: 001-66676 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 5, 2016

12 3 4 5 6 7...33

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与CY7C1442KV33相关器件

型号	品牌	获取价格	描述	数据表
CY7C1442KV33-250AXC	CYPRESS	获取价格	Cache SRAM, 2MX18, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100
CY7C1442V33-200AC	CYPRESS	获取价格	Cache SRAM, 2MX18, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1442V33-200BGC	CYPRESS	获取价格	Cache SRAM, 2MX18, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1442V33-300BZC	CYPRESS	获取价格	Cache SRAM, 2MX18, 2.3ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165
CY7C144-35AC	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C144-35AI	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C144-35AIT	CYPRESS	获取价格	Dual-Port SRAM, 8KX8, 35ns, CMOS, PQFP64, 14 X 14 MM, 1.4 MM HEIGHT, PLASTIC, TQFP-64
CY7C144-35JC	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C144-35JCR	CYPRESS	获取价格	Dual-Port SRAM, 8KX8, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C144-35JCT	CYPRESS	获取价格	Dual-Port SRAM, 8KX8, 35ns, CMOS, PQCC68, PLASTIC, LCC-68

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