Datasheet > CY7C1442V33-200BGC

CY7C1442V33-200BGC

更新时间： 2024-10-26 14:51:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
35页	970K
描述
Cache SRAM, 2MX18, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

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CY7C1442V33-200BGC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119	针数：	119
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
Is Samacsys：	N	Base Number Matches：	1

CY7C1442V33-200BGC 数据手册

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440V33

CY7C1440V33

CY7C1442V33

PRELIMINARY

CY7C1446V33

1M x 36 / 2M x 18 / 512K x 72 Pipelined SRAM

inputs include all addresses, all data inputs, address-pipelin-

ing Chip Enable (CE), burst control inputs (ADSC, ADSP, and

Features

• Fast clock speed: 300, 250, 200, and 167 MHz

• Provide high-performance 3-1-1-1 access rate

• Fast access time: 2.3, 2.7, 3.0 and 3.5 ns

• Optimal for depth expansion

• Single 3.3V –5% and +5% power supply V_DD

• Separate V_DDQfor 3.3V or 2.5V

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Chip Enable for address pipeline

ADV), write enables (BWa, BWb, BWc, BWd and BWE), and

Global Write (GW).

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). The data (DQ_a,b,c,d) and the data

parity (DP_a,b,c,d) outputs, enabled by OE, are also asynchro-

nous.

DQ_a,b,c,dand DP_a,b,c,dapply to CY7C1440V33, DQ_{a,b,c,d,e,f,g,h}

and DP_{a,b,c,d,e,f,g,h}apply to CY7C1446V33 and DQ_a,band

DP_a,bapply to CY7C1442V33. a, b, c, d, e, f, g, h each are 8

bits wide in the case of DQ and 1 bit wide in the case of DP.

• Address, data, and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst se-

quence)

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address Status Controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance Pin (ADV).

• Automatic power-down for portable applications

• High-density, high-speed packages

• JTAG boundary scan for BGA packaging version

• Available in 119-bump BG,165-ball FBGA package and

100-pin TQFP packages (CY7C1440V33 and

CY7C1442V33) 209 FBGA package for CY7C1446V33

Address, data inputs, and write controls are registered on-chip

to initiate self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the write control inputs. Indi-

vidual Byte Write allows individual bytes to be written. BWa

controls DQa and DPa. BWb controls DQ and DP . BWc con-

trols DQc and DPd. BWd controls DQ and DPd. BWe controls

DQe and DPe. BWf controls DQf and DPf. BWg controls DQg

and DPg. BWh controls DQh and DPh. BWa, BWb, BWc,

BWd, BWe, BWf, BWg and BWh can be active only with BWE

being LOW. GW being LOW causes all bytes to be written.

Write pass-through capability allows written data available at

the output for the immediately next Read cycle. This device

also incorporates a pipelined enable circuit for easy depth ex-

pansion without penalizing system performance.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced sin-

gle-layer polysilicon, triple-layer metal technology. Each mem-

ory cell consists of six transistors.

The CY7C1440V33, CY7C1442V33, and CY7C1446V33

SRAMs integrate 1,048,576 x 36 / 2,097,152 x18 and 524,288

x 72 SRAM cells with advanced synchronous peripheral cir-

cuitry and a 2-bit counter for internal burst operation. All syn-

chronous inputs are gated by registers controlled by a posi-

tive-edge-triggered Clock Input (CLK). The synchronous

All inputs and outputs of the CY7C1440V33, CY7C1442V33

and the CY7C1446V33 are JEDEC standard JESD8-5 com-

patible.

Selection Guide

CY7C1440V33 CY7C1440V33 CY7C1440V33 CY7C1440V33

CY7C1442V33 CY7C1442V33 CY7C1442V33 CY7C1442V33

CY7C1446V33 CY7C1446V33 CY7C1446V33 CY7C1446V33

-300

-250

-200

-167

Maximum Access Time (ns)

2.2

2.4

3.1

3.5

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Com’l

TBD

Cypress Semiconductor Corporation

Document #: 38-05184 Rev. **

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised April 8, 2002

12 3 4 5 6 7...35

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与CY7C1442V33-200BGC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1442V33-300BZC	CYPRESS	获取价格	Cache SRAM, 2MX18, 2.3ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165
CY7C144-35AC	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C144-35AI	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C144-35AIT	CYPRESS	获取价格	Dual-Port SRAM, 8KX8, 35ns, CMOS, PQFP64, 14 X 14 MM, 1.4 MM HEIGHT, PLASTIC, TQFP-64
CY7C144-35JC	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C144-35JCR	CYPRESS	获取价格	Dual-Port SRAM, 8KX8, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C144-35JCT	CYPRESS	获取价格	Dual-Port SRAM, 8KX8, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C144-35JCT	ROCHESTER	获取价格	8KX8 DUAL-PORT SRAM, 35ns, PQCC68, PLASTIC, LCC-68
CY7C144-35JI	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C144-35JIR	CYPRESS	获取价格	暂无描述

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