5秒后页面跳转
CY7C1441KV33-133AXM PDF预览

CY7C1441KV33-133AXM

更新时间: 2024-11-27 21:14:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
31页 3025K
描述
Cache SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-144

CY7C1441KV33-133AXM 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:LQFP,Reach Compliance Code:compliant
ECCN代码:3A001.A.2.CHTS代码:8542.32.00.41
风险等级:5.74最长访问时间:6.5 ns
其他特性:FLOW-THROUGH ARCHITECTUREJESD-30 代码:R-PQFP-G100
长度:20 mm内存密度:37748736 bit
内存集成电路类型:CACHE SRAM内存宽度:36
功能数量:1端子数量:100
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:1MX36
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

CY7C1441KV33-133AXM 数据手册

 浏览型号CY7C1441KV33-133AXM的Datasheet PDF文件第2页浏览型号CY7C1441KV33-133AXM的Datasheet PDF文件第3页浏览型号CY7C1441KV33-133AXM的Datasheet PDF文件第4页浏览型号CY7C1441KV33-133AXM的Datasheet PDF文件第5页浏览型号CY7C1441KV33-133AXM的Datasheet PDF文件第6页浏览型号CY7C1441KV33-133AXM的Datasheet PDF文件第7页 
CY7C1441KV33  
Military Temperature, 36-Mbit (1M × 36)  
Flow-Through SRAM  
Military Temperature, 36-Mbit (1M  
× 36) Flow-Through SRAM  
Features  
Functional Description  
Supports 133-MHz bus operations  
1M × 36 common I/O  
The CY7C1441KV33 is 3.3 V, 1M × 36 synchronous  
flow-through SRAMs, respectively designed to interface with  
high-speed microprocessors with minimum glue logic. Maximum  
access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit  
on-chip counter captures the first address in a burst and  
increments the address automatically for the rest of the burst  
access. All synchronous inputs are gated by registers controlled  
3.3 V core power supply  
2.5 V or 3.3 V I/O power supply  
Fast clock-to-output times  
6.5 ns (133 MHz version)  
by  
a
positive-edge-triggered Clock (CLK) input. The  
synchronous inputs include all addresses, all data inputs,  
address-pipelining Chip Enable (CE1), depth-expansion Chip  
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and  
ADV), Write Enables (BWx, and BWE), and Global Write (GW).  
Asynchronous inputs include the Output Enable (OE) and the ZZ  
pin.  
Provide high-performance 2-1-1-1 access rate  
User-selectable burst counter supporting interleaved or linear  
burst sequences  
Separate processor and controller address strobes  
Synchronous self-timed write  
The CY7C1441KV33 allows either interleaved or linear burst  
sequences, selected by the MODE input pin. A HIGH selects an  
interleaved burst sequence, while a LOW selects a linear burst  
sequence. Burst accesses can be initiated with the Processor  
Address Strobe (ADSP) or the cache Controller Address Strobe  
(ADSC) inputs. Address advancement is controlled by the  
Address Advancement (ADV) input.  
Asynchronous output enable  
CY7C1441KV33 is available in JEDEC-standard 100-pin  
TQFP and 165-ball FBGA Pb-free packages.  
IEEE 1149.1 JTAG-Compatible Boundary Scan  
“ZZ” Sleep Mode option  
Available in Military Temperature Range  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or Address  
Strobe Controller (ADSC) are active. Subsequent burst  
addresses can be internally generated as controlled by the  
Advance pin (ADV).  
The CY7C1441KV33 operates from a +3.3 V core power supply  
while all outputs may operate with either a +2.5 V or +3.3 V  
supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
Description  
Maximum access time  
133 MHz  
6.5  
Unit  
ns  
Maximum operating current  
× 36  
180  
mA  
Cypress Semiconductor Corporation  
Document Number: 002-12701 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 19, 2016  

与CY7C1441KV33-133AXM相关器件

型号 品牌 获取价格 描述 数据表
CY7C1441KV33-133BZM INFINEON

获取价格

Synchronous SRAM
CY7C1441KV33-133BZXI CYPRESS

获取价格

36-Mbit (1M × 36/2M × 18) Flow-Through SRAM
CY7C1441KVE33 CYPRESS

获取价格

36-Mbit (1M × 36/2M × 18) Flow-Through SRAM
CY7C1441KVE33-133AXC CYPRESS

获取价格

36-Mbit (1M × 36/2M × 18) Flow-Through SRAM
CY7C1441KVE33-133AXC INFINEON

获取价格

Synchronous SRAM with ECC
CY7C1441KVE33-133AXI INFINEON

获取价格

Synchronous SRAM with ECC
CY7C1441V25-133BGC CYPRESS

获取价格

Standard SRAM, 1MX36, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1441V25-133BZC CYPRESS

获取价格

Standard SRAM, 1MX36, 6.5ns, CMOS, PBGA165, 15 X 17 MM, FBGA-165
CY7C1441V25-150AC CYPRESS

获取价格

Standard SRAM, 1MX36, 5.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1441V33 ETC

获取价格

Memory