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CY7C1441V33-150BGC PDF预览

CY7C1441V33-150BGC

更新时间： 2024-11-20 19:57:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
28页 605K
描述
Standard SRAM, 1MX36, 5.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

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CY7C1441V33-150BGC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.92最长访问时间：5.5 ns
其他特性：FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK)：150 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：37748736 bit内存集成电路类型：STANDARD SRAM
内存宽度：36功能数量：1
端子数量：119字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：2.4 mm
最小待机电流：3.14 V子类别：SRAMs
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

CY7C1441V33-150BGC 数据手册

 浏览型号CY7C1441V33-150BGC的Datasheet PDF文件第2页浏览型号CY7C1441V33-150BGC的Datasheet PDF文件第3页浏览型号CY7C1441V33-150BGC的Datasheet PDF文件第4页浏览型号CY7C1441V33-150BGC的Datasheet PDF文件第5页浏览型号CY7C1441V33-150BGC的Datasheet PDF文件第6页浏览型号CY7C1441V33-150BGC的Datasheet PDF文件第7页 
CY7C1441V33  
CY7C1443V33  
CY7C1447V33  
PRELIMINARY  
1M x 36/2M x 18/512K x 72  
Flow-through SRAM  
inputs include all addresses, all data inputs, address-pipelining  
Chip Enable (CE), Burst Control Inputs (ADSC, ADSP, and  
ADV), Write Enables (BWa, BWb, BWc, BWd, BWe, BWf, BWg,  
BWh, and BWe), and Global Write (GW).  
Features  
• Supports 133-MHz bus operations  
• 1M x 36/2M x 18/512K x 72 common I/O  
• Fast clock-to-output times  
— 6.5 ns (for 133-MHz device)  
— 7.5 ns (for 117-MHz device)  
Asynchronous inputs include the Output Enable (OE) and  
Burst Mode Control (MODE). The data outputs (DQ), enabled  
by OE, are also asynchronous.  
• Single 3.3V –5% and +5% power supply VDD  
• Separate VDDQ for 3.3V or 2.5V  
• Byte Write Enable and Global Write control  
• Burst Capability – linear or interleaved burst order  
Addresses and chip enables are registered with either  
Address Status Processor (ADSP) or address status controller  
(ADSC) input pins. Subsequent burst addresses can be inter-  
nally generated as controlled by the Burst Advance Pin (ADV).  
Address, data inputs, and write controls are registered on-chip  
to initiate self-timed Write cycle. Write cycles can be one to  
four bytes wide as controlled by the write control inputs.  
Individual byte write allows individual byte to be written. BWa  
controls DQ1–DQ8 and DP1. BWb controls DQ9–DQ16 and  
DP2. BWc controls DQ17–DQ24 and DP3. BWd controls  
DQ25–DQ32 and DP4. BWe controls DQ33–DQ40 and DP5.  
BWf controls DQ41–DQ48 and DP6. BWg controls  
DQ49–DQ56 and DP7. BWh controls DQ57–DQ64 and DP8.  
BWa, BWb, BWc, BWd, BWe, BWf, BWg, and BWh can be  
active only with BWE being LOW. GW being LOW causes all  
bytes to be written. Write pass-through capability allows  
written data available at the output for the immediately next  
Read cycle. This device also incorporates pipelined enable  
circuit for easy depth expansion without penalizing system  
performance.  
• Automatic power down available using ZZ mode or CE  
deselect  
• JTAG boundary scan for BGA packaging version  
• Available in 119-ball bump BGA, 165-ball FBGA, and  
100-pin TQFP packages (CY7C1441V33 and  
CY7C1443V33). 209 FBGA package for CY7C1447V33.  
Functional Description  
The Cypress Synchronous Burst SRAM family employs  
high-speed, low power CMOS designs using advanced  
single-layer polysilicon, triple-layer metal technology. Each  
memory cell consists of six transistors.  
The CY7C1441V33/CY7C1443V33/CY7C1447V33 SRAMs  
integrate 1,048,576 x 36/2,097,152 x18 and 524,288 x 72  
SRAM cells with advanced synchronous peripheral circuitry  
and a two-bit counter for internal burst operation. All  
synchronous inputs are gated by registers controlled by a  
positive-edge-triggered clock input (CLK). The synchronous  
All inputs and outputs of theCY7C1441V33/CY7C1443V33/  
CY7C1447V33 are JEDEC-standard JESD8-5-compatible.  
Logic Block Diagram CY7C1441V33 – 1M × 36  
MODE  
2
(A[1;0]  
)
Q
Q
CLK  
ADV  
ADSC  
0
BURST  
COUNTER  
CE  
CLR  
1
ADSP  
Q
18  
20  
ADDRESS  
REGISTER  
CE  
D
1M X36  
A[19:0]  
GW  
20  
18  
MEMORY  
ARRAY  
DQd, DPd  
BYTEWRITE  
REGISTERS  
D
Q
BWE  
BW  
d
DQc, DPc  
BYTEWRITE  
REGISTERS  
D
D
D
Q
Q
Q
BW  
c
DQb, DPb  
BYTEWRITE  
REGISTERS  
BW  
b
DQa, DPa  
BYTEWRITE  
REGISTERS  
BW  
a
36  
36  
CE  
CE  
1
2
D
D
Q
ENABLE CE  
REGISTER  
CE  
3
Q
OUTPUT  
REGISTERS  
INPUT  
REGISTERS  
CLK  
ENABLE DELAY  
REGISTER  
CLK  
OE  
ZZ  
SLEEP  
CONTROL  
DQa,b,c,d  
DPa,b,c,d  
Cypress Semiconductor Corporation  
Document #: 38-05185 Rev. *B  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised November 13, 2002  
1234567...28

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