Datasheet > 存储 > SRAM> CY7C144-25AXC

CY7C144-25AXC

更新时间： 2024-11-24 05:09:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
20页	609K
描述
8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY

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CY7C144-25AXC 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MS-026, TQFP-64
针数：	64	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.41
Factory Lead Time：	1 week	风险等级：	5.72
最长访问时间：	25 ns	其他特性：	AUTOMATIC POWER-DOWN
I/O 类型：	COMMON	JESD-30 代码：	S-PQFP-G64
JESD-609代码：	e4	长度：	14 mm
内存密度：	65536 bit	内存集成电路类型：	DUAL-PORT SRAM
内存宽度：	8	湿度敏感等级：	3
功能数量：	1	端口数量：	2
端子数量：	64	字数：	8192 words
字数代码：	8000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	8KX8	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP64,.66SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大待机电流：	0.015 A	最小待机电流：	4.5 V
子类别：	SRAMs	最大压摆率：	0.18 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	20	宽度：	14 mm
Base Number Matches：	1

CY7C144-25AXC 数据手册

CY7C144 CY7C1458K

with SEM, INT, BUSY

x 8/9 Dual-Port Static RAM

CY7C144

CY7C145

8K x 8/9 Dual-Port Static RAM

with SEM, INT, BUSY

are included on the CY7C144/5 to handle situations when

multiple processors access the same piece of data. Two ports

are provided permitting independent, asynchronous access

for reads and writes to any location in memory. The

CY7C144/5 can be utilized as a standalone 64/72-Kbit

dual-port static RAM or multiple devices can be combined in

order to function as a 16/18-bit or wider master/slave dual-port

static RAM. An M/S pin is provided for implementing 16/18-bit

or wider memory applications without the need for separate

master and slave devices or additional discrete logic. Appli-

cation areas include interprocessor/multiprocessor designs,

Features

• TrueDual-Portedmemorycellsthatallowsimultaneous

reads of the same memory location

• 8K x 8 organization (CY7C144)

• 8K x 9 organization (CY7C145)

• 0.65-micron CMOS for optimum speed/power

• High-speed access: 15ns

• Low operating power: I_CC= 160 mA (max.)

• Fully asynchronous operation

• Automatic power-down

communications

status

buffering,

and

dual-port

video/graphics memory.

Each port has independent control pins: chip enable (CE),

read or write enable (R/W), and output enable (OE). Two flags,

BUSY and INT, are provided on each port. BUSY signals that

the port is trying to access the same location currently being

accessed by the other port. The interrupt flag (INT) permits

communication between ports or systems by means of a mail

box. The semaphores are used to pass a flag, or token, from

one port to the other to indicate that a shared resource is in

use. The semaphore logic is comprised of eight shared

latches. Only one side can control the latch (semaphore) at

any time. Control of a semaphore indicates that a shared

resource is in use. An automatic power-down feature is

controlled independently on each port by a chip enable (CE)

pin or SEM pin.

• TTL compatible

• Master/Slave select pin allows bus width expansion to

16/18 bits or more

• Busy arbitration scheme provided

• Semaphores included to permit software handshaking

between ports

• INT flag for port-to-port communication

• Available in 68-pin PLCC, 64-pin and 80-pin TQFP

• Pb-Free packages available

Functional Description

The CY7C144 and CY7C145 are high-speed CMOS 8K x 8

and 8K x 9 dual-port static RAMs. Various arbitration schemes

Logic Block Diagram

R/W

(7C145) I/O

I/O (7C145)

I/O

CONTROL

I/O

CONTROL

I/O

[1, 2]

BUSY

12L

12R

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS

DECODER

INTERRUPT

SEMAPHORE

ARBITRATION

R/W

SEM

[2]

INT

INT [2]

M/S

Notes:

1. BUSY is an output in master mode and an input in slave mode.

2. Interrupt: push-pull output and requires no pull-up resistor.

Cypress Semiconductor Corporation

Document #: 38-06034 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 6, 2005

12 3 4 5 6 7...20

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CY7C144-25AXC 替代型号

型号	品牌	替代类型	描述	数据表
CY7C144AV-25AXC	CYPRESS	类似代替	3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
CY7C144AV-25AC	CYPRESS	类似代替	3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
CY7C144-55AXC	CYPRESS	类似代替	8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY

与CY7C144-25AXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C144-25JC	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C144-25JCR	CYPRESS	获取价格	Dual-Port SRAM, 8KX8, 25ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C144-25JI	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C144-25JIR	CYPRESS	获取价格	Dual-Port SRAM, 8KX8, 25ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C1442AV25	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1442AV25-167AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1442AV25-167AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1442AV25-167BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1442AV25-167BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1442AV25-167BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

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