Datasheet > CY7C1346F

CY7C1346F

更新时间： 2024-11-21 05:09:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
16页	322K
描述
2-Mbit (64K x 36) Pipelined Sync SRAM

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CY7C1346F 数据手册

CY7C1346F

2-Mbit (64K x 36) Pipelined Sync SRAM

Features

Functional Description^[1]

• Registered inputs and outputs for pipelined operation

• 64K × 36 common I/O architecture

• 3.3V core power supply

• 3.3V I/O operation

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 100-MHz device)

The CY7C1346F SRAM integrates 65,536 x 36 SRAM cells

with advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(

), depth-expansion Chip Enables (CE and

), Burst

CE₃

CE₁

Control inputs (

and

ADSC ADSP

), Write Enables

ADV

(

, and

), and Global Write (

BWE

). Asynchronous

BW_[A:D]

inputs include the Output Enable ( ) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

• Provide high-performance 3-1-1-1 access rate

clock when either Address Strobe Processor (

) or

ADSP

• User-selectable burst counter supporting Intel^

Address Strobe Controller (

) are active. Subsequent

ADSC

Pentium^interleaved or linear burst sequences

burst addresses can be internally generated as controlled by

the Advance pin ( ).

ADV

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Offered in JEDEC-standard 100-pin TQFP package

• “ZZ” Sleep Mode Option

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

controlled by the Byte Write control inputs.

when active

causes all bytes to be written.

LOW

The CY7C1346F operates from a +3.3V core power supply

while all outputs also operate with a +3.3V supply. All inputs

and outputs are JEDEC-standard JESD8-5-compatible.

Logic Block Diagram

A0, A1, A

ADDRESS

A[1:0]

MODE

ADV

CLK

BURST

COUNTER

AND

CLR

LOGIC

ADSC

ADSP

DQ^D,DQ

BYTE

WRITE REGISTER

BYTE

WRITE DRIVER

D ,DQPD

BYTE

WRITE DRIVER

C ,DQPC

BYTE

WRITE REGISTER

C,DQPC

DQs

DQP

OUTPUT

BUFFERS

OUTPUT

REGISTERS

MEMORY

ARRAY

SENSE

AMPS

DQ^B,DQP

DQP

BYTE

WRITE DRIVER

BYTE

WRITE REGISTER

DQP

DQA,DQP

A ,DQPA

BYTE

WRITE DRIVER

BYTE

WRITE REGISTER

BWE

INPUT

REGISTERS

ENABLE

PIPELINED

ENABLE

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05384 Rev. *B

Revised December 3, 2004

12 3 4 5 6 7...16

中文翻译

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与CY7C1346F相关器件

型号	品牌	获取价格	描述	数据表
CY7C1346F-100AC	CYPRESS	获取价格	2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346F-100ACT	CYPRESS	获取价格	Cache SRAM, 64KX36, 4.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1346F-133AC	CYPRESS	获取价格	2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346F-133ACT	CYPRESS	获取价格	Cache SRAM, 64KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1346F-166AC	CYPRESS	获取价格	2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346F-166ACT	CYPRESS	获取价格	Cache SRAM, 64KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1346H	CYPRESS	获取价格	2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346H-133AXC	CYPRESS	获取价格	Cache SRAM, 64KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM, LEAD FREE, PLASTIC, TQFP-100
CY7C1346H-133AXI	CYPRESS	获取价格	Cache SRAM, 64KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM, LEAD FREE, PLASTIC, TQFP-100
CY7C1346H-166AXC	CYPRESS	获取价格	2-Mbit (64K x 36) Pipelined Sync SRAM

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